====== SmartLogic ======

The SmartLogic project turns a [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.2.e.html|ZTEX USB-FPGA-Module 1.2]] into a flexible smart card research tool that allows complete control over the smart card communication channel for eavesdropping, man-in-the-middle attacks, relaying and card emulation.

===== References =====
  * **[[https://code.google.com/p/smartlogictool/|SmartLogic source code (Google Code)]]**

===== Introduction =====

{{:en:projects:setup_fpgacard_web.png|SmartLogic Setup}}

This project uses
  * the [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.2.e.html|ZTEX USB-FPGA-Module 1.2]]
  * the [[http://www.ztex.de/usb-fpga-1/pwr-1.0.e.html|Power Supply Module]] for USB-FPGA boards
  * the [[http://scuba.sourceforge.net/|SCUBA smart card project]] (included in the source)
  * a generic smart card reader
  * a smart card interface to connect to the pins of the FPGA board

===== Example Setup =====

==== Trace of Card Balance Read Out (Dutch Chipknip) ====
{{:en:projects:smartlogic:trace_chipknip_small.gif|Trace of the Dutch Chipknip}}

==== The SmartLogic ====
{{:en:projects:smartlogic:smartlogic_01.png|}}
{{:en:projects:smartlogic:smartlogic_02.png|}}

==== The Generic Reader ====
{{:en:projects:smartlogic:reader.png|}}