====== High speed FPGA configuration ======

The following ZTEX FPGA Boards support different configuration speeds:

^ FPGA Board  ^ Low speed (via EP0)  ^ High speed (via bulk Endpoint)  ^ 
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.13.e.html|USB-FPGA Modules 2.13]]  | about 0.6 MByte/s  | up to 24 MByte/s  |
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.14.e.html|USB-FPGA Modules 2.14]]  | about 3 MByte/s  | up to 26 MByte/s  |
| [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Modules 2.16]]  | about 0.6 MByte/s  | up to 24 MByte/s  |
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.18.e.html|USB-FPGA Modules 2.18]]  | about 3 MByte/s  | up to 26 MByte/s  |

High speed configuration is supported by [[en:software:default_firmware|Default Firmware]]. 

This page describes how to enable enable it in user specific firmware for EZ-USB FX2 and FX3 based FPGA Boards.

===== Enabling high speed FPGA configuration for EZ-USB FX2 =====
Two macros must be called in order to enable high speed FPGA configuration:

<code c>
EP_CONFIG(<EPNUM>,<IFNUM>,BULK,OUT,512,<BUFNUM>);	 
ENABLE_HS_FPGA_CONF(<EPNUM>);
</code>

''EP_CONFIG'' defines an Endpoint where ''<EPNUM>'' stands for the Endpoint number (valid values: 2, 4, 6 , 8), ''<IFNUM>'' for the interface number
(valid values: 0, 1, 2, 3) and ''<BUFNUM>'' for the number of buffers (valid values: 2, 3, 4). After the configuration the Endpoint can be used for other purposes. 

''ENABLE_HS_FPGA_CONF'' defines the Endpoint which shall be used for the high speed configuration.

A typical example looks like 
<code c>
// Endpoint 2 is used to high speed FPGA configuration
EP_CONFIG(2,0,BULK,OUT,512,2);	 

// enables high speed FPGA configuration, use EP 2
ENABLE_HS_FPGA_CONF(2);
</code>

===== Enabling high speed FPGA configuration for EZ-USB FX3 =====
In FX3 firmware there are different methods to enable high speed FPGA configuration, but due to a bug in Cypress SDK it is recommended to create a dedicated
Endpoint for FPGA configuration. Suggested method is:

<code c>
// defines endpoint number for FPGA configuration. Modify it if desired.
#define ZTEX_FPGA_CONF_FAST_EP	6  

// the interface to which the endpoint belongs
#define ZTEX_FPGA_CONF_FAST_IFACE 1

// a free PIB socket
#define ZTEX_FPGA_CONF_FAST_SOCKET CY_U3P_PIB_SOCKET_5

// endpoint settings
#define EP_SETUP  \
    INTERFACE(0, ... ) // application specific endpoint settings \
        INTERFACE(1,   // configuration endpoint settings \
	EP_BULK(ZTEX_FPGA_CONF_FAST_EP, OUT, 1, \
	    DMA(dma_fpga_conf_handle, CY_U3P_DMA_TYPE_AUTO, 1, 2 , ZTEX_FPGA_CONF_FAST_SOCKET, \
		CB(0,0) \
	    ) \
	) \
    ) 
</code>

In this example interface 1 with Endpoint 6 is created and only used for FPGA configuration. It is also possible to assign the Endpoint to interface 0.  To re-use the enpoint is supported by the ZTEX SDK, Cypress SDK may fail in super speed mode.