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Slave-FIFO Autoin

, 2011/05/25 14:45

Hi everybody,

I have got the usb module and I would like to implement a slave autoin fifo. The only differences with the example given in 9.3.10 of the documentation is that i would like the polarity of fifo pins to be high, the wordsize to be 16bits, an external clock and to use the end point 2.

However, my code doesn't work with the FPGA i programmed but worse, when i change FIFOPINPOLAR from 0x3F to 0x00, the polarity doesn't actually change (i checked with an oscillocope).

You will find my code after this message. Could you please tell me if you notice something wrong with it.

Thanks in advance,

Fabien


  #include[ztex.h]
  EP_CONFIG(2,0,BULK,IN,512,2);
  void main(void)	
  {
      /*// init everything*/
      init_USB();
      IFCONFIG = 0x3; //Configure pins for fifo mode (see page 222), 
      SYNCDELAY;
      REVCTL = 0x03; 
      SYNCDELAY;
  
      // Reset Fifo.
      FIFORESET = 0x80;
      SYNCDELAY;
      FIFORESET = 0x82;
      SYNCDELAY;
      FIFORESET = 0x84;
      SYNCDELAY;
      FIFORESET = 0x86;
      SYNCDELAY;
      FIFORESET = 0x88;
      SYNCDELAY;
      FIFORESET = 0x00;
      SYNCDELAY;
  
      // Make the USB auto commit in packets
      // EPxFIFOCFG = ~AUTOOUT, AUTOIN, ZEROLEN, WORLDWIDE; (p237)
      EP2FIFOCFG = 0x0D; 
      SYNCDELAY;
      PINFLAGSAB = 0x00;
      SYNCDELAY;
      PINFLAGSCD = 0x00;
      SYNCDELAY;
      PORTACFG = 0x00;
      SYNCDELAY;
      FIFOPINPOLAR = 0x3F;
      SYNCDELAY;
      EP2AUTOINLENH = 0x02;  //512 bytes packet size
      SYNCDELAY;
      EP2AUTOINLENL = 0x00;
      SYNCDELAY; 
  
      while (1) {}
  }

Discussion

stefan, 2011/05/25 18:24

Hi Fabien,

there is an AUTOIN example, infifo, in the SDK package. Did you tried its settings?

For example, the order in which the configuration registers are set is important. You first reset the FIFO (why do you reset the FIFO's for EP 4..8?) and configure it afterwards. That is probably wrong.

Regards Stefan

test88.246.68.183, 2011/05/30 21:31

Hi Stefan,

I could not find the infifo example in the SDK. Could you be more specific?

Thanks

stefan, 2011/05/30 21:51

Hi Burhan,

it is named 'infifo'

Regards Stefan

test88.246.68.183, 2011/05/30 22:00

Hi Stefan,

I could not find any file or folder named infifo in the SDK. I just downloaded a fresh copy of the SDK and searched it.

stefan, 2011/05/30 22:10

Sorry, the correct name is 'intraffic'. It can be found in examples/usb-fpga-*/*/intraffic .

, 2012/07/14 05:14

Hi,stefan I have two questions about USB-FPGA moudle 1.15x. The first one, I have a test about the IFCLK, when I set “IFCONFIG = bmBIT7 | bmBIT5 |3” in macro like this #define[POST_FPGA_CONFIG][POST_FPGA_CONFIG

IOA7 = 1;				// reset on
OEA |= bmBIT7;
IOC0 = 0;				// controlled mode
OEC |= bmBIT0;
  
EP2CS &= ~bmBIT0;			// clear stall bit

EP6CS &= ~bmBIT0;			// clear stall bit
  
REVCTL = 0x3;
SYNCDELAY; 
IFCONFIG = bmBIT7 | bmBIT5 |3;	        // internel 48MHz clock, drive IFCLK ouput, slave FIFO interface
SYNCDELAY; 
EP6FIFOCFG = bmBIT3 | bmBIT0;           // AOTUOIN, WORDWIDE
SYNCDELAY;
EP2FIFOCFG = bmBIT4 |bmBIT0;             //AOTOOUT,WORDWIDE
  SYNCDELAY;

#ifdef[fastmode]

EP6AUTOINLENH = 4;                 	// 1024 bytes 

#else

EP6AUTOINLENH = 2;                 	// 512 bytes 

#endif

SYNCDELAY;
EP6AUTOINLENL = 0;
SYNCDELAY;
FIFORESET = 0x80;			// reset FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
OUTPKTEND = 0x82;           //Arm both EP2 buffers to "prime the pump"
SYNCDELAY;
OUTPKTEND = 0x82;
FIFOPINPOLAR = 0;
SYNCDELAY; 
PINFLAGSAB = 0;
SYNCDELAY; 
PINFLAGSCD = 0;
SYNCDELAY; 
IOA7 = 0;				// reset off

]

, the FXCLK won't work, but if I set it in the main function like this void main(void) {

  init_USB(); 
  IFCONFIG = bmBIT7 | bmBIT5 |3;	        // internel 48MHz clock, drive IFCLK ouput, slave FIFO interface
while (1) {	
  }

}, it works. what's the matter please? The sencond question, when I changed the firmware and download it to 68013 use the .jar file , the new firmware won't work and the working one is the old, but if I Power off and then download the new firmware ,it work well. Is there some turn for the operating please? Thanks

, 2012/07/14 05:37

Oh, sorry ,there is somthing wrong with the question, “FXCLK won't work should be changed to “IFCLK won't work”, thx.

ip84.181.58.68, 2012/07/25 16:56

Question 1: The commands in the macro 'POST_FPGA_CONFIG' are executed after uploading the bitstream via USB. It will not work if you use JTAG. Also make sure the the commands in the macro are executed (e.g. using the general purpose LED on your 1.15x FPGA board).

Question 2: It is probably an error in the initialization sequence if the FIFO interface, i.e. transition from old firmware to new firmware does not work properly.

, 2012/12/17 18:19

Hello,

I'm having trouble opening up a new discussion (no option to do so on the end of the Discussion Page?!) so I'll add my question in here: I am trying to get a „simple“ Synchronous Slave FIFO with Auto-in/out to work like follows: I have written a VHDL state machine which should read the command it get's from the ez-usb as soon as the according FLAG(ep not empty) is set. After that it should get some Data(1 byte) to the FIFO that gets read with libusb. But everytime I try to read the byte from the endpoint I am getting the following libusb error : _usb_reap_async My guess is that there either is no Datato be read from the Endpoint (State Machine is wrong) or that I have missed something in the firmware. I would post my code but I am not sure if I really should do it in this thread or in my own(if I would know how to do that)…

Thanks in advance

ip84.181.54.128, 2012/12/17 18:28

The access right problem is fixed now.

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en/discussions/slave-fifo_autoin.txt · Last modified: 2011/05/25 16:57 by 138.246.2.47
 
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