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Slave-FIFO Autoout

, 2011/02/18 21:41

Hi Guys,

I'm having problems setting up the AUTOOUT feature on the FX2 with the FPGA-Board 1.2. I've been trying to get things running for three days now with no luck.

Here's the setup:

1) FX2 configuration
  IFCONFIG = 0xA3; SYNCDELAY;
  FIFOPINPOLAR = 0x00; SYNCDELAY; // All fifo pins low active
  EP2CFG = 0xA0; SYNCDELAY;
  EP2FIFOCFG = 0x01; SYNCDELAY; 
  FIFORESET = 0x80; SYNCDELAY; // NAK all transfers
  FIFORESET = 0x02; SYNCDELAY; // Reset FIFO EP2
  FIFORESET = 0x00; SYNCDELAY; // Restore normal operation
  
  OUTPKTEND = 0x82; SYNCDELAY; // Skip one outpacket on EP2
  OUTPKTEND = 0x82; SYNCDELAY; // Skip one outpacket on EP2

  // Zero to one for AUTOOUT enable
  EP2FIFOCFG = 0x11; SYNCDELAY;

The device uses EP2 configured as BULK output with 4x 512 byte buffers and 16 bit output. After the configuration the CPU is held in idle (while(1){}). The FX2-FIFO is set to be clocked internally by the 48 MHz clock. The external FX2 control-pins SLOE and SLRD are low active.

2) FPGA configuration

I build a state-machine in VHDL to continuously read the data from the HOST by the FPGA. The pins SLRD and SLOE are asserted (set to 0) until the (low-active) FIFO_EMPTY flag of the FX2 is falling from 1 to 0. By using Chip-Scope one can clearly see that the FIFO_EMPTY is asserted every 256 clock cycles.

3) HOST configuration

I'm using libusb under Ubuntu Linux continously calling usb_bulk_write with messages of 512 bytes each.

The problem is that the sampled data is always equal to the first sample send by the host, i.e. when sending the sequence 0,1,2,3…255 the FPGA always receives 0,0,0,….0 (read using chipscope). Setting the first value to any other number lets the FPGA receive that number but the FIFO data pointer somehow does not increment.

I'm puzzled about the result and whatever I do (and I tried a bunch of things!) I can't get the FX2 AUTOOUT feature working. Any ideas?

Discussion

stefan, 2011/02/19 01:18

Hi,

in section 9.3.4 of the TRM you find some example code for AUTOIN transfers.

There are certain issues:

  1. you forgot `REVCTL = 3;'
  2. you only arm 2 of 4 buffers, i.e. you have to call `OUTPKTEND = 0x82;' four times
  3. EP2FIFOCFG is set twice, omit `EP2FIFOCFG = 0x01; SYNCDELAY;' on line 4

Please try this. If it does not work, please send your full firmware source.

Regards Stefan

test94.216.214.68, 2011/02/19 11:10

Hi Stefan,

thank you for your quick reply. AUTOIN is no problem. AUTOOUT does not work.

  • I tried setting REVCTL = 3; With REVCTL.1=1 the FX2 does not work at all (USB timeout).
  • I armed all buffers by OUTPKTEND = 0x82; It makes no difference.
  • The reason for EP2FIFOCFG being set twice is a bug in the FX2. Otherwise the the AUTOOUT bit can not be set to 1 (e.g. see: http://coding.derkeiler.com/Archive/General/comp.arch.embedded/2007-01/msg01409.html). Additionally, with this setting the REVCTL.1 bit does not have to be set to 1.

Actually, the code i've posted is the full firmware source and is placed after the ZTEX init_USB(); routine.

It's no problem letting the HOST continously send packets to the FX2. The behaviour is all as expected (such as timeouts on the host side when the FPGA stops reading).

The issue is that the data on FD[15:0] is not valid and always equal to the first sample sent by the HOST via usb_bulk_write.

Cheers, Michael

stefan, 2011/02/21 10:31

Hi Michael,

section 9.3.4 of the TRM also contains AUTOOUT code.

I tried setting REVCTL = 3; With REVCTL.1=1 the FX2 does not work at all (USB timeout).

In the examples (intraffic and memtest) REVCTL=3; works.

If you set you set REVCTL.1=1 you must arm all buffers. If you set REVCTL.1=0 you must not arm the buffers.

Actually, the code i've posted is the full firmware source and is placed after the ZTEX init_USB(); routine.

A proper initialization procedure is required since the EZ-USB behavior is unpredictable if the control pins are in a invalid state. You should wait with the FIFO configuration until the FPGA is in configured.

If you upload the bitstream via EZ-USB the code belongs in the POST_FPGA_CONFIG macro (see the examples) and a reset pin (PA0 in the examples) is recommended.

If you upload the bitstream via JTAG you have to implement something that says the EZ-USB the the FPGA is waiting for input.

If it does not work please send the full firmware and hdl code since there are also some other pitfalls.

Regards Stefan

ip178.200.26.27, 2012/08/02 00:04

Hello Michael,

Did you find a solution to this problem. I have thesame situation and i have been searching for a month now without luck. The usb_fd bus does not change its value. It shoes invalid values attimes too (7D99). Please share with me if u found the solution.

Thanks Mathias

, 2012/07/09 12:09

Dear Stefan,

I would like to ask about setting the wordwide in asynchronous slave FIFO read (autoout = 1). Here is my firmware setup:

#include[ztex-conf.h]
#include[ztex-utils.h]

EP_CONFIG(2,0,BULK,IN,512,4);
EP_CONFIG(6,0,BULK,OUT,512,2);

IDENTITY_UFM_1_15(10.13.0.0,0);
#define[PRODUCT_STRING]["OUT Traffic experiment"]

ENABLE_HS_FPGA_CONF(6);

#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
IOA7 = 1;				// reset on
OEA |= bmBIT7;
IOC0 = 0;				// controlled mode
OEC = 1;

EP2CS &= ~bmBIT0;			// clear stall bit
      EP6CS &= ~bmBIT0;			// clear stall bit
  
REVCTL = 0x3;
SYNCDELAY; 

IFCONFIG = bmBIT7 | bmBIT5 | 3;	        // internel 30MHz clock, drive IFCLK ouput, asynch,slave FIFO interface
SYNCDELAY; 
EP2FIFOCFG = bmBIT3;    // AOTUOIN, WORDWIDE
      SYNCDELAY;
      EP6FIFOCFG = 0x10;      // AOTUOOUT, WORDWIDE
SYNCDELAY;
  
#ifdef[fastmode]
EP2AUTOINLENH = 4;                 	// 1024 bytes 
#else	
EP2AUTOINLENH = 2;                 	// 512 bytes 
#endif	
SYNCDELAY;
EP2AUTOINLENL = 0;
SYNCDELAY;

FIFORESET = 0x80;			// reset FIFO
SYNCDELAY;
FIFORESET = 0x82;
SYNCDELAY;
      FIFORESET = 0x86;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
      OUTPKTEND = 0x86;
      SYNCDELAY;
      OUTPKTEND = 0x86;
      SYNCDELAY;

FIFOPINPOLAR = 0;
SYNCDELAY; 
PINFLAGSAB = 0;
SYNCDELAY; 
PINFLAGSCD = 0;
SYNCDELAY; 

IOA7 = 0;				// reset off
]

#include[ztex.h]

void main(void)	
{
  init_USB();

  while (1) {	
  }
}

I meant to set EP6 as an auto out FIFO (EP6FIFOCFG = 0x10;) with 8 bit word mode. Supposedly the 'FD' signal in the vhdl should work with 8 bit width (std_logic_vector(7 downto 0)), but it didn't! So i tried some other way an finally come up to test it using 16 bit wide 'FD' (std_logic_vector(15 downto 0)), and it works! Now I'm puzzled. How come the wordwide become 16 bit?

EP2 initializations in the firmware are actually not used. My big plan is to get the device as both autoin and autoout FIFO (but currently testing it with autoout). Do you see any fault in my code?

Regards, David

ip79.197.127.38, 2012/07/11 12:31
Now I'm puzzled. How come the wordwide become 16 bit?

No clue what is going on there. Even more strange: EP6 is (re-)used for high speed configurations. In this mode the interface operates with 8 bit.

Try to remove the line “ENABLE_HS_FPGA_CONF(6);” in order to disable high speed configuration. The EZ-USB has sometimes problems with changing the FIFO settings.

If you play around with different bus widths, make sure that you upload the firmware every time you change it. (Use the ”-f” parameter if you derived you code from an example.)

, 2012/07/13 05:02

Hi,

Thanks for the answer. I have tried to remove “ENABLE_HS_FPGA_CONF(6);” but method LibusbJava.usb_bulk_write returned a -116 instead. I think the firmware always get uploaded properly because I always see “Firmware upload time: ….ms” in the console.

And here is something even more strange: when I set EP6FIFOCFG = 0x11; (autoout 16 bit), the device act as if it wants to send 32 bit! (which is not possible?). For example, if I send 5 byte data containing 0x01,0x02,0x03,0x04,0x05 (first byte 0x01 to last byte 0x05). Then if I set the FD signal as 16 bit (15 downto 0), the fpga will receive 0x01,0x02,0x05! And if I set FD signal as 8 bit (7 downto 0), the fpga will receive 0x01,0x05.

I'm testing it by storing the bytes received by the fpga in a temporary variable. Then I drive several IO pins on the board to represent that temporary variable (I use voltmeter to see the bits). BTW, I'm using FPGA module 1.15 attached on board 1.3. Also I use SDCC 3.0.0 on win Xp sp3. Any more idea?

Regards, David

ip84.181.62.120, 2012/07/13 09:56
Thanks for the answer. I have tried to remove “ENABLE_HS_FPGA_CONF(6);” but method LibusbJava.usb_bulk_write returned a -116 instead.

This means there is a problem with with your initialization code, i.e. your initialization code does not work without the initialization sequence for high speed configuration.

Regards Stefan

ip98.211.158.123, 2012/09/12 01:50

Has anyone found an answer to this questions??? I'm trying to set up slave FIFOs 4 and 6 for IN and OUT respectively. However when I try to write from the host I get the following error. –> Error: Error sending data: libusb0-dll:err [submit_async] submitting request failed, win error: The parameter is incorrect.

Here is my firmware code

#include[ztex-conf.h]

#include[ztex-utils.h]

EP_CONFIG(4,0,BULK,IN,512,4); EP_CONFIG(6,0,BULK,OUT,512,4);

IDENTITY_UFM_1_11(10.12.0.0,0);

#define[PRODUCT_STRING][“intraffic example for UFM 1.11”]

#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG

OEC = 255;			// clear stall bit
  
REVCTL = 0x3;
SYNCDELAY;
 	
 	// set the slave FIFO interface to 48MHz
 	IFCONFIG |= 0x40;   	
 	SYNCDELAY;
	
//ENDPOINT2 CONFIGURATION
SYNCDELAY;
EP4FIFOCFG = 0x08; // EP4 is AUTOOUT=0, AUTOIN=1, ZEROLEN=0, WORDWIDE=0
       SYNCDELAY;
 	EP4AUTOINLENH = 2; // 512 bytes 	

SYNCDELAY;
OUTPKTEND = 0x06;  // Arm both EP6 buffers to “prime the pump”

//ENDPOINT6 CONFIGURATION
SYNCDELAY;
EP6FIFOCFG = 0x10; 		// EP6 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
SYNCDELAY;
EP6AUTOINLENH = 2;                 	// 512 bytes 
		
SYNCDELAY;	
PINFLAGSAB = 0x00; 	// defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY; 		// FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00; 	// FLAGC as empty flag, as pointed to by FIFOADR[1:0]
			// won't generally need FLAGD
PORTACFG = 0x00; 	         // used PA7/FLAGD as a port pin, not as a FIFO flag
SYNCDELAY;

EP6FIFOPFH = 0x80; 	// you can define the programmable flag (FLAGA)
SYNCDELAY; 		// to be active at the level you wish
EP6FIFOPFL = 0x00;
SYNCDELAY;

IOA0 = 0;				// reset off

]

include the main part of the firmware kit, define the descriptors, … #include[ztex.h] void main(void) { WORD i,size; init everything

  init_USB();

while (1) {

  }

}

ip84.181.56.25, 2013/01/03 07:55

Hi,

Has anyone found an answer to this questions???

To which questions?

libusb0-dll:err [submit_async] submitting request failed, win error: The parameter is incorrect.

Typically this indicates incompatibility between USB settings (defined in the firmware) and host software.

Regards Stefan

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en/discussions/slave-fifo_autoout.txt · Last modified: 2011/02/18 23:07 by 129.187.155.207
 
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