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en:projects:smartlogic [2011/07/12 12:47] – [Short Introduction] 131.174.142.235 | en:projects:smartlogic [2011/07/12 13:31] (current) – [Introduction] 131.174.142.235 | ||
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* a smart card interface to connect to the pins of the FPGA board | * a smart card interface to connect to the pins of the FPGA board | ||
+ | ===== Example Setup ===== | ||
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+ | ==== Trace of Card Balance Read Out (Dutch Chipknip) ==== | ||
+ | {{: | ||
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+ | ==== The SmartLogic ==== | ||
+ | {{: | ||
+ | {{: | ||
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+ | ==== The Generic Reader ==== | ||
+ | {{: |