This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revision | Last revisionBoth sides next revision | ||
en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2014/07/15 21:46] – stefan | en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2016/09/11 14:10] – stefan | ||
---|---|---|---|
Line 1: | Line 1: | ||
- | ====== High speed configuration ====== | + | ====== High speed FPGA configuration ====== |
The following ZTEX FPGA Boards support different configuration speeds: | The following ZTEX FPGA Boards support different configuration speeds: | ||
^ FPGA Board ^ Low speed (via EP0) ^ High speed (via bulk Endpoint) | ^ FPGA Board ^ Low speed (via EP0) ^ High speed (via bulk Endpoint) | ||
- | | [[http:// | + | | [[http:// |
- | | [[http:// | + | | [[http:// |
- | | [[http:// | + | | [[http:// |
- | | [[http:// | + | |
- | | [[http:// | + | |
- | The high speed configuration | + | High speed configuration |
+ | |||
+ | This page describes how to enable enable it in user specific firmware for EZ-USB FX2 and FX3 based FPGA Boards. | ||
+ | |||
+ | ===== Enabling high speed FPGA configuration for EZ-USB FX2 ===== | ||
+ | Two macros must be called in order to enable | ||
<code c> | <code c> | ||
Line 31: | Line 34: | ||
</ | </ | ||
- | If '' | + | ===== Enabling high speed FPGA configuration |
+ | In FX3 firmware there are different methods to enable high speed FPGA configuration, | ||
+ | Endpoint for FPGA configuration. Suggested method is: | ||
- | Details about the CPLD (including source | + | <code c> |
+ | // defines endpoint number for FPGA configuration. Modify | ||
+ | #define ZTEX_FPGA_CONF_FAST_EP 6 | ||
+ | |||
+ | // the interface to which the endpoint belongs | ||
+ | #define ZTEX_FPGA_CONF_FAST_IFACE 1 | ||
+ | |||
+ | // a free PIB socket | ||
+ | #define ZTEX_FPGA_CONF_FAST_SOCKET CY_U3P_PIB_SOCKET_5 | ||
+ | |||
+ | // endpoint settings | ||
+ | #define EP_SETUP | ||
+ | INTERFACE(0, | ||
+ | INTERFACE(1, | ||
+ | EP_BULK(ZTEX_FPGA_CONF_FAST_EP, | ||
+ | DMA(dma_fpga_conf_handle, | ||
+ | CB(0,0) \ | ||
+ | ) \ | ||
+ | ) \ | ||
+ | ) | ||
+ | </ | ||
+ | In this example interface 1 with Endpoint 6 is created and only used for FPGA configuration. It is also possible to assign the Endpoint to interface 0. To re-use the enpoint is supported by the ZTEX SDK, Cypress SDK may fail in super speed mode. |