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en:ztex_boards:ztex_fpga_boards:jtag [2011/01/03 14:32] – The JTAG connector is only 8 pins, not 9 146.103.254.11 | en:ztex_boards:ztex_fpga_boards:jtag [2013/11/25 20:00] (current) – stefan | ||
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====== JTAG ====== | ====== JTAG ====== | ||
- | The FPGA's on [[http:// | + | The FPGA's on all ZTEX USB-FPGA Modules |
- | ^ Pin ^ Description ^ | + | ===== Series 2 FPGA Boards ===== |
- | | 1 | +3.3V | | + | JTAG signals on all [[http:// |
- | | 2 | +2.5V | | + | |
- | | 3 | Not connected | | + | |
- | | 4 | TMS | | + | |
- | | 5 | TCK | | + | |
- | | 6 | TDI | | + | |
- | | 7 | TDO | | + | |
- | | 8 | GND | | + | |
- | The I/O voltage for the JTAG signals | + | No firmware |
- | In order to enable | + | ===== Series 1 FPGA Boards ===== |
+ | JTAG signals on [[http:// | ||
- | If the JTAG interface is used it may be helpful to upload a Firmware (e.g. the [[standalone|standalone example Firmware]]) to the EEPROM in order to avoid to reload a Firmware every time the device is powered up. | + | [[http:// |
+ | have on-board JTAG headers. | ||
+ | In order to enable JTAG configuration the PROG_B pin of the FPGA which is connected to bit 1 of port A of the EZ-USB must be driven high. This happens automatically if a Firmware developed with the SDK is installed. | ||
+ | If the JTAG interface is used it may be helpful to upload a Firmware (e.g. the [[standalone|standalone example Firmware]]) to the EEPROM in order to avoid to reload a Firmware every time the device is powered up. | ||
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