[[Memory tutorial for USB-FPGA-Modules 1.11]]
 
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en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2011/12/07 20:28] – 84.181.93.233en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2012/02/09 17:32] (current) – stefan
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 TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.833333 ns HIGH 50 %; TIMESPEC "TS_FXCLK" = PERIOD "FXCLK" 20.833333 ns HIGH 50 %;
 NET "FXCLK"  LOC = "K14" | IOSTANDARD = LVCMOS33 ; NET "FXCLK"  LOC = "K14" | IOSTANDARD = LVCMOS33 ;
- 
-############################################################################ 
-# VCC AUX VOLTAGE  
-############################################################################ 
-CONFIG VCCAUX=2.5; 
  
 ############################################################################ ############################################################################
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 ===== Insert the Core into your VHDL code ===== ===== Insert the Core into your VHDL code =====
-Please uses ''memtest.vhd'' as reference for the following instructions.+Please use ''memtest.vhd'' from the memory test example as reference.
  
     - Add the following inputs/outputs to the entity declaration: <code vhdl>     - Add the following inputs/outputs to the entity declaration: <code vhdl>
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 ===== Setup the clock resource ===== ===== Setup the clock resource =====
  
-On [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|ZTEX UBS-FPGA Modules 1.11]] the memory clock is generated from the 48 MHz output clock of the EZ-USB. Unfortunately the memory interface generator (MIG) expects that the memory clock comes from an external pin (at least up to version 3.5).+On [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|ZTEX USB-FPGA Modules 1.11]] the memory clock is generated from the 48 MHz output clock of the EZ-USB. Unfortunately the memory interface generator (MIG) expects that the memory clock comes from an external pin (at least up to version 3.5).
 The common case that the clock is generated from another clock is ignored by the MIG. The common case that the clock is generated from another clock is ignored by the MIG.
  
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 RESET0 <= RESET_IN or (not DCM0_LOCKED) or DCM0_CLK_STATUS(2); RESET0 <= RESET_IN or (not DCM0_LOCKED) or DCM0_CLK_STATUS(2);
 </code> </code>
-  - Apply the changes / patch listed below to to ''ipcore_dir/<ipcore name>/user_design/rtl/memc3_infrastructure.vhd'', i.e. remove all global input buffer (IBUFG) stuff and replace ''CLKIN1 => sys_clk_ibufg'' by ''CLKIN1 => sys_clk'' This allows to connect an internally generated clock to the input of the PLL instance used for the generation of MCB clocks: <code>+  - Apply the changes / patch listed below to to ''ipcore_dir/<ipcore name>/user_design/rtl/memc3_infrastructure.vhd'', i.e. remove all global input buffer (IBUFG) stuff and replace ''CLKIN1 => sys_clk_ibufg'' by ''CLKIN1 => sys_clk'' This allows to connect an internally generated clock to the input of the PLL instance used for the generation of MCB clocks. The .diff file can be found in the memtest example as ''ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd.diff''. <code>
 --- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200 --- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200
 +++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200 +++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200
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 === Example 3: 132 MHz memory clock (low power setup) ===  === Example 3: 132 MHz memory clock (low power setup) === 
-The memory device and the parallel (on-chip) input termination of the FPGA usually draws a lot of power (about 1.5W). By reducing the +The memory and the parallel (on-chip) input termination of the FPGA consumes about 1.8W at maximum frequency. By reducing the 
-memory frequency to 132 MHz and by disabling the parallel termination the power consumption can be drastically reduced. (The memory bandwidth of this setting is 528 MByte/s, more than enough for the most application.)+memory frequency to 132 MHz and by disabling the parallel termination the power consumption can be drastically reduced. (The memory bandwidth of this setting is 528 MByte/s.)
  
-For this setting the ''MT46V32M16XX-6'' should be chosen instead of the ''MT46V32M16XX-5B-IT'' and the clock period must be set to 7500 ps (step 7 in the section "Creating the IP Core").+For this setting the ''MT46V32M16XX-6'' should be chosen instead of the ''MT46V32M16XX-5B-IT'' and the clock period should be set to 7500 ps (step 7 in the section "Creating the IP Core").
  
 The parallel termination can be disabled by commenting out the following lines in the ucf file: The parallel termination can be disabled by commenting out the following lines in the ucf file:
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-{{indexmenu_n>5000}}+{{indexmenu_n>5010}}
  
 
en/ztex_boards/ztex_fpga_boards/memory_tutorial_1_11.txt · Last modified: 2012/02/09 17:32 by stefan
 
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