Differences

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--- en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/02/15 14:00] – [Memory clock generation by modification of the MCB PLL] 84.181.58.125
+++ en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2017/02/04 19:42] (current) – stefan
@@ Line 10: / Line 10: @@
   - Choose ''IP Core Generator'' and enter a name for the new Core
   - Select ''Memories & Storage Elements'' -> ''Memory Interface Generators'' -> ''MIG'' and click on ''NEXT'' -> ''FINISH''
-  - Verify the Settings in the first dialog box (USB-FPGA Module 1.15a: xc6slx45-ftg256, speed grade -2; 1.15b: xc6slx75-ftg256; speed grade -3, 1.15d: xc6slx150-ftg256, speed grade -3): \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-01.png|USB-FPGA Module 1.15, MIG screen 1}}
+  - Verify the Settings in the first dialog box (USB-FPGA Module 1.15a: xc6slx45-CSG484, speed grade -2; 1.15b: xc6slx75-CSG484; speed grade -3, 1.15d: xc6slx150-CSG484, speed grade -3): \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-01.png|USB-FPGA Module 1.15, MIG screen 1}}
   - Select "Create Design"\\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-02.png|USB-FPGA Module 1.15, MIG screen 2}}
   - The settings on the next screen can be ignored: \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-03.png|USB-FPGA Module 1.15, MIG screen 3}}
@@ Line 375: / Line 375: @@
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-~~DISCUSSION~~