===== Logic Analyzer =====

The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis.

This is a slightly modified version of [[http://gadgetforge.gadgetfactory.net/gf/project/lax/|Sump]]. Since there is no problem to investigate external signals, sync module was removed. This has increased the max clock speed and slightly reduced footprint.

===== Download and build =====

  * download [[http://www.strijar.ru/ztex/la.tar.gz|archive]]
  * unpack it

For build do:

  make

===== EZ-USB FX2 Firmware =====

No special firmware is required in order to run LA. The [[en:ztex_boards:ztex_fpga_boards:standalone|standalone firmware]] from the ZTEX SDK can be used as dummy firmware and to allow Bitstream uploading via USB.

===== Load bitstream =====

The bitstream can be uploaded via USB using [[en:software:FWLoader]] or via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] using Xilinx Impact.

===== Connect serial console =====

For work with LA a serial adapter cable need to be connected to the FPGA Board.

By default, the serial port is connected to the following pins:

^ Name  ^ FPGA ball  ^  Pin of the FPGA Board  ^ Pin at the Experimental board  ^
| TX  | C13  | A13  | A13  |
| RX  | A14  | A12  | A12  |

If other pins are preferred, lines around line 6 need to be changed. Default baud rate is **921600** specified in the file top.vhd

===== Client =====

Best to use an [[https://lxtreme.nl/projects/ols/|alternate client.]] Download it and unpack. After start select "Capture" in menu, then "Begin capture". Or press <Ctrl-B>. Select your serial port and baud rate, then press "Capture" button.

[[Client screenshot|{{http://www.strijar.ru/ztex/la_screen.png}}]]

Here you see the test signals are generated in top.vhd:

  process (clock) begin
    if rising_edge(clock) then
      if rst = '1' then
        counter <= (others => '0');
        shift <= "10110000";
      else
        counter <= counter + 1;
        shift <= shift(6 downto 0) & shift(7);
      end if;
    end if;
  end process;
  
  input(7 downto 0) <= counter;
  input(8) <= clk;
  input(9) <= shift(0);