JOP - Java Optimized Processor - is one way to use a configurable Java processor in small embedded real-time systems. It shall help to increase the acceptance of Java for these systems.

This project explains how a JOP processor can be implemented on a ZTEX USB-FPGA Module 1.11c with Spartan6 LX25 FPGA. Currently only 16MB the DDR RAM (of 64MB) are supported. The FPGA utilization is about 23% which allows to build multiple cores in CMP JOP.

The latest version can be obtained from with following Git command:

git clone https://github.com/jop-devel/jop

Create the needed directories with:

make directories

The tools are built with following make command:

make tools

The JVM configured to download the Java application from the serial interface is built with:

make jopser

By default the JOP build is set up to use the quartus tools so the make command will fail with quartus_map: Command not found. This is ok.

Open the file xilinx/ztex/ise_13/ise_13.xise. Once the project has loaded you will get a dialog asking you for the path for a few files. These files will be generate in the next step so dismiss the dialog for now.

The sources for the MIG has to be added to the project. Add the file xilinx/ztex/mig_37/mig_37.xco and the icon for the u_mig37 “file” should change from a question mark to a light bulb. TODO: Why is this needed? -Trygve

First the project has to be configure to generate VHDL instead of Verilog. Open the Design Properties dialog (Project → Design Properties) and make sure “Preferred Language” is “VHDL” instead of “Verilog”. TODO: It should be possible to check in this change to git - trygve

Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file xilinx/ztex/mig_37/mig_37.xco for Coregen

• Component Name: mig_37
• Bank 3 Memory Type DDR SDRAM
• Frequency: 200MHz
• Memory Part: MT46V32M16XX-5B-IT
• Configuration Selection: One 32-bit bi-directional port
• Memory Address Mapping Selection: Row, Bank, Column

Once the controller is generated copy all the VHDL files from the xilinx/ztex/mig_37/mig_37/user_design/rtl/*.vhd directory to xilinx/ztex/mig_37 directory and apply patch:

patch < memc3_infrastructure.patch

Run make in directory xilinx/ztex or load project xilinx/ztex/ise_13/ise_13.xise to ISE

No special firmware is required in order to run JOP. The standalone firmware from the ZTEX SDK can be used as dummy firmware and to allow Bitstream uploading via USB.

The bitstream can be uploaded via USB using FWLoader or via JTAG using Xilinx Impact.

In order to verify the functionality of the JOP a serial adapter cable need to be connected to the FPGA Board.

By default, the serial port is connected to the following pins:

If other pins are preferred, lines around line 11 nedd to be changed.

From root directory of jop make:

make japp -e P1=bench P2=jbe P3=DoAll

Copy file java/target/dist/bin/DoAll.jop to root jop dir and load it:

• for Win:

  down.exe -e DoAll.jop com3

• for Linux:

  ./down -e DoAll.jop /dev/ttyUSB0

Provide your correct port!

Result:

Parsed JOP file ok.
* 11656 words of Java bytecode (45 KB)
* 20315 words external RAM (79 KB)

Transmitting data via serial...
[########################################################### ] 20224 / 20315
Done.
JOP start V 20110107
93 MHz, 16384 KB RAM, 1 CPUs
JavaBenchEmbedded V1.1
Micro Benchmarks:
iload_3 iadd 46091000 1/s
iinc 23172000 1/s
ldc 4629000 1/s
if_icmplt taken 15477000 1/s
if_icmplt not taken 15477000 1/s
getfield 2699000 1/s
getstatic 5084000 1/s
iaload 2122000 1/s
invoke 521679 1/s
invokestatic 667033 1/s
invokeinterface 413802 1/s
Kernel Benchmarks:
Sieve 3663 1/s
Application benchmarks:
Kfl 8555 1/s
UdpIp 3980 1/s
Lift 9346 1/s