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en:projects:jop [2011/07/06 11:15] – 84.181.78.148 | en:projects:jop [2011/07/18 13:19] – trygvis | ||
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- | ====== Running JOP (Java Optimized Processor) on a ZTEX FPGA Board ====== | + | ===== Running JOP (Java Optimized Processor) on a ZTEX FPGA Board ===== |
[[http:// | [[http:// | ||
- | This project explains how a JOP processor can be implemented on a [[http:// | + | This project explains how a JOP processor can be implemented on a [[http:// |
- | multiple cores in CMP JOP. | + | |
===== Download the fresh Source ===== | ===== Download the fresh Source ===== | ||
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< | < | ||
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+ | By default the JOP build is set up to use the quartus tools so the make command will fail with '' | ||
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+ | ===== Open the project in ISE ===== | ||
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+ | Open the file '' | ||
+ | |||
+ | The sources for the MIG has to be added to the project. Add the file '' | ||
===== Create the Spartan-6 DDR memory interface ===== | ===== Create the Spartan-6 DDR memory interface ===== | ||
- | Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file xilinx/ | + | First the project has to be configure to generate VHDL instead of Verilog. Open the Design Properties dialog (Project -> Design Properties) and make sure " |
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+ | Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file '' | ||
* Component Name: mig_37 | * Component Name: mig_37 | ||
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* Memory Address Mapping Selection: Row, Bank, Column | * Memory Address Mapping Selection: Row, Bank, Column | ||
- | Once the controller is generated copy all the VHDL files from the user_design/ | + | Once the controller is generated copy all the VHDL files from the '' |
< | < |