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--- en:ztex_boards:ztex_fpga_boards:standalone [2022/03/23 09:04] – [Hints for Vivado] stefan
+++ en:ztex_boards:ztex_fpga_boards:standalone [2022/03/23 09:10] – [Hints for Vivado] stefan
@@ Line 30: / Line 30: @@
 With the default bitstream settings of Vivado configuration from SPI Flash may not work. The required setting can be found in the constraints file ''constraints/usb-fpga-2.xdc'' of the SDK
 <code tcl>
-set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
-set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
@@ Line 37: / Line 36: @@
 </code>
+By default, Xilinx Series 7 FPGA's read the data at the wrong edge which means that the clock speed must be halved. For maximum configuration speed, you can enforce reading at the falling edge using the constraints
+<code tcl>
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design] ;# (optional)
+</code>
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