<?xml version="1.0" encoding="UTF-8"?>
<!-- generator="FeedCreator 1.8" -->
<?xml-stylesheet href="https://wiki.ztex.de/lib/exe/css.php?s=feed" type="text/css"?>
<rss version="2.0">
    <channel xmlns:g="http://base.google.com/ns/1.0">
        <title>ZTEX Wiki</title>
        <description></description>
        <link>https://wiki.ztex.de/</link>
        <lastBuildDate>Mon, 06 Apr 2026 09:54:54 +0000</lastBuildDate>
        <generator>FeedCreator 1.8</generator>
        <image>
            <url>https://wiki.ztex.de/lib/tpl/sidebar/images/favicon.ico</url>
            <title>ZTEX Wiki</title>
            <link>https://wiki.ztex.de/</link>
        </image>
        <item>
            <title>Memory tutorial for USB-FPGA-Modules 2.12, 2.13, 2.14 and 2. ...</title>
            <link>https://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:memfifo:usb_fpga_2_13&amp;rev=1698700836&amp;do=diff</link>
            <description>Memory tutorial for USB-FPGA-Modules 2.12, 2.13, 2.14 and 2.18

This tutorial explains the generation of the memory controller IP Core for for the memfifo Example USB-FPGA-Modules 2.12,
USB-FPGA-Modules 2.13, USB-FPGA-Modules 2.14 and USB-FPGA-Modules 2.18.

Creating the IP Core

This section describes how the IP Core is created using MIG version 2.1 (Viavado Version 14.2). 
The settings for other versions should be very similar.</description>
            <author>anonymous@undisclosed.example.com (Anonymous)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 21:20:36 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-03.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-03.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699322&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=300&amp;t=1698699322&amp;amp;tok=1b3466&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-03.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-03.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:22 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-06.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-06.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699322&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=318&amp;t=1698699322&amp;amp;tok=e183cf&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-06.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-06.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:22 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-04.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-04.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699321&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=296&amp;t=1698699321&amp;amp;tok=d30a5f&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-04.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-04.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:21 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-08.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-08.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699321&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=296&amp;t=1698699321&amp;amp;tok=f81cfd&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-08.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-08.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:21 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-11.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-11.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699321&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=296&amp;t=1698699321&amp;amp;tok=eff610&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-11.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-11.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:21 +0000</pubDate>
        </item>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-10.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-10.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699320&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=296&amp;t=1698699320&amp;amp;tok=945e0f&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-10.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-10.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:20 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-09.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-09.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699320&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=296&amp;t=1698699320&amp;amp;tok=771f3f&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-09.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-09.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:55:20 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-12.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-12.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699012&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=395&amp;h=500&amp;t=1698699012&amp;amp;tok=2ebc94&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-12.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-12.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:50:12 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-07.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-07.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699010&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=430&amp;t=1698699010&amp;amp;tok=c57221&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-07.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-07.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:50:10 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-05.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-05.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699010&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=389&amp;t=1698699010&amp;amp;tok=e70ab8&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-05.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-05.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:50:10 +0000</pubDate>
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            <title>en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-02.png</title>
            <link>https://wiki.ztex.de/doku.php?image=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo%3Aa7-ddr3-02.png&amp;ns=en%3Aztex_boards%3Aztex_fpga_boards%3Amemfifo&amp;rev=1698699008&amp;tab_details=history&amp;mediado=diff&amp;do=media</link>
            <description>&lt;img src=&quot;https://wiki.ztex.de/lib/exe/fetch.php?w=499&amp;h=306&amp;t=1698699008&amp;amp;tok=197d5f&amp;amp;media=en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-02.png&quot; alt=&quot;en:ztex_boards:ztex_fpga_boards:memfifo:a7-ddr3-02.png&quot; /&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards:memfifo</category>
            <pubDate>Mon, 30 Oct 2023 20:50:08 +0000</pubDate>
        </item>
        <item>
            <title>Default Firmware - [HDL Modules] </title>
            <link>https://wiki.ztex.de/doku.php?id=en:software:default_firmware&amp;rev=1698697588&amp;do=diff</link>
            <description>Default Firmware

The ZTEX SDK includes Default Firmwares for all Series 2 FPGA Boards. They define a set of compatible features:

	*  Bitstream uploading to volatile and non-volatile memory
	*  Communication interface:
		*  Hi-speed bi-directional interface operating at maximum possible data rate of the hardware</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:software</category>
            <pubDate>Mon, 30 Oct 2023 20:26:28 +0000</pubDate>
        </item>
        <item>
            <title>Projects and examples</title>
            <link>https://wiki.ztex.de/doku.php?id=en:projects:start&amp;rev=1698697506&amp;do=diff</link>
            <description>Projects and examples

This section is intended for the presentation of example projects.

Examples from the SDK

A lot of examples can be found in the ZTEX SDK package.

Just one of it is presented here in order to give an impression about the Usage of the ZTEX SDK.</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:projects</category>
            <pubDate>Mon, 30 Oct 2023 20:25:06 +0000</pubDate>
        </item>
        <item>
            <title>en:projects:btcminer - removed</title>
            <link>https://wiki.ztex.de/doku.php?id=en:projects:btcminer&amp;rev=1698697337&amp;do=diff</link>
            <description></description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:projects</category>
            <pubDate>Mon, 30 Oct 2023 20:22:17 +0000</pubDate>
        </item>
        <item>
            <title>Flash access from FPGA</title>
            <link>https://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:flash_acces_from_fpga&amp;rev=1698697302&amp;do=diff</link>
            <description>Flash access from FPGA

Flash memory of ZTEX Series 2 FPGA boards can be accessed from the USB controller and from FPGA. Since release 20231030, the SDK contains a framework which avoids concurrent accesses to Flash.

This page describes the different scenarios.</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards</category>
            <pubDate>Mon, 30 Oct 2023 20:21:42 +0000</pubDate>
        </item>
        <item>
            <title>ZTEX FPGA Boards - [Articles] </title>
            <link>https://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:ztex_fpga_boards&amp;rev=1698687472&amp;do=diff</link>
            <description>ZTEX FPGA Boards

Articles

	*  memfifo example
		*  Memory tutorial for USB-FPGA Module 2.04
		*  Memory tutorial for USB-FPGA Module 2.13

	*  JTAG  
	*  Standalone apllications
	*  Memory tutorial for USB-FPGA Modules 1.11
	*  Memory tutorial for USB-FPGA Modules 1.15
	*  USB Powering
	*  Flash access from FPGA
	*  High speed configuration
	*  Porting to USB-FPGA Modules 1.15y
	*  Bitstream Encryption
	*  Indirect Programming of SPI Flash
	*  SD-card support on Series 2 FPGA Boards</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards</category>
            <pubDate>Mon, 30 Oct 2023 17:37:52 +0000</pubDate>
        </item>
        <item>
            <title>Indirect Programming of SPI Flash via FPGA</title>
            <link>https://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:indirect_flash_programming&amp;rev=1698687359&amp;do=diff</link>
            <description>Indirect Programming of SPI Flash via FPGA

ZTEX Series 2 FPGA Board have SPI Flash memory that can be used to store the Bitstream. Most comfortable way to write data to Flash is to use the SDK (DeviceServer, FWLoader or the API). Nevertheless, on EZ-USB FX2 based FPGA Boards the SPI Flash can also be programmed indirectly through JTAG and FPGA using the Xilinx tools.</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards</category>
            <pubDate>Mon, 30 Oct 2023 17:35:59 +0000</pubDate>
        </item>
        <item>
            <title>FWLoader - [Ordered options] </title>
            <link>https://wiki.ztex.de/doku.php?id=en:software:fwloader&amp;rev=1698687129&amp;do=diff</link>
            <description>FWLoader

FWLoader is the Firmware and Bitstream upload utility of the EZ-USB SDK.

Usage

There are two ways of starting FWLoader. Either by executing the bash script FWLoader in the directory java/FWLoader of the SDK package 
or by calling

java -cp [&lt;path to&gt;]FWLoader.jar FWLoader &lt;options&gt;</description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:software</category>
            <pubDate>Mon, 30 Oct 2023 17:32:09 +0000</pubDate>
        </item>
        <item>
            <title>en:ztex_boards:ztex_fpga_boards:cluster_power_supplies - removed</title>
            <link>https://wiki.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:cluster_power_supplies&amp;rev=1698682838&amp;do=diff</link>
            <description></description>
            <author>stefan@undisclosed.example.com (stefan)</author>
        <category>en:ztex_boards:ztex_fpga_boards</category>
            <pubDate>Mon, 30 Oct 2023 16:20:38 +0000</pubDate>
        </item>
    </channel>
</rss>
