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--- en:projects:smartlogic [2011/07/12 12:47] – [Short Introduction] 131.174.142.235
+++ en:projects:smartlogic [2011/07/12 13:31] (current) – [Introduction] 131.174.142.235
@@ Line 17: / Line 17: @@
   * a smart card interface to connect to the pins of the FPGA board
+===== Example Setup =====
+==== Trace of Card Balance Read Out (Dutch Chipknip) ====
+{{:en:projects:smartlogic:trace_chipknip_small.gif|Trace of the Dutch Chipknip}}
+==== The SmartLogic ====
+{{:en:projects:smartlogic:smartlogic_01.png|}}
+{{:en:projects:smartlogic:smartlogic_02.png|}}
+==== The Generic Reader ====
+{{:en:projects:smartlogic:reader.png|}}