The ZTEX SDK includes Default Firmwares for all Series 2 FPGA Boards. They define a set of compatible features:
The feature-rich communication interface makes firmware development obsolete in may cases, e.g. most examples of the SDK use default firmwares. Because all functions are compatible the host software can be made board independent.
A more detailed overview is given by the following block diagram
There are 3 HDL modules which are located in directory
default/fpga-fx[2|3]/ of the SDK:
|Module Name||Description||Used in this examples|
| ||bi-directional high-speed interface||memfifo|
| ||SRAM like low speed interface||ucecho|
| ||GPIO's and reset signal||memfifo, ucecho|
This module implements the the high-speed communication for both directions using the EZ-USB Slave FIFO interface (FX2) or GPIF2 (FX3). It provides the following features:
The interface is compatible for all FPGA Boards and listed below. A brief description is given in the comments. The hardware pins are omitted because they depend from the EZ-USB variant and are directly connected to the interface of the top level module. In order to learn more about the usage please take a look into the top level module of the memfifo examle.
module ezusb_io #( parameter OUTEP = 2, // FX2 only: Endpoint for FPGA -> EZ-USB transfers parameter INEP = 6 , // FX2 only: Endpoint for EZ-USB -> FPGA transfers parameter TARGET = "" // FX2 only: Target FPGA: "A7": Artix 7, "" all others ) ( output ifclk, // buffered output of the interface clock // this is the clock for the user logic input reset, // asynchronous reset input output reset_out, // synchronous reset output // FPGA pins that are connected directly to EZ-USB are omitted here // Signals for FPGA -> EZ-USB transfer. The are controlled by user logic. input [15:0] DI, // data written to EZ-USB input DI_valid, // 1 indicates valid data; DI and DI_valid must be hold if DI_ready is 0 output DI_ready, // 1 if new data are accepted input DI_enable, // setting to 0 disables FPGA -> EZ-USB transfers input [15:0] pktend_timeout, // timeout in multiples of 65536 clocks before a short packet committed // setting to 0 disables this feature // Signals for EZ-USB -> FPGA transfer. They are controlled by user logic. output reg [15:0] DO, // data read from EZ-USB output reg DO_valid, // 1 indicates valid data input DO_ready, // setting to 1 enables writing new data to DO in next clock // DO and DO_valid are hold if DO_ready is 0 // set to 0 to disable data reads // debug output output [3:0] status );