The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis.
This is a slightly modified version of Sump. Since there is no problem to investigate external signals, sync module was removed. This has increased the max clock speed and slightly reduced footprint.
For build do:
No special firmware is required in order to run LA. The standalone firmware from the ZTEX SDK can be used as dummy firmware and to allow Bitstream uploading via USB.
For work with LA a serial adapter cable need to be connected to the FPGA Board.
By default, the serial port is connected to the following pins:
|Name||FPGA ball||Pin of the FPGA Board||Pin at the Experimental board|
If other pins are preferred, lines around line 6 need to be changed. Default baud rate is 921600 specified in the file top.vhd
Best to use an alternate client. Download it and unpack. After start select “Capture” in menu, then “Begin capture”. Or press <Ctrl-B>. Select your serial port and baud rate, then press “Capture” button.
Here you see the test signals are generated in top.vhd:
process (clock) begin if rising_edge(clock) then if rst = '1' then counter <= (others => '0'); shift <= "10110000"; else counter <= counter + 1; shift <= shift(6 downto 0) & shift(7); end if; end if; end process; input(7 downto 0) <= counter; input(8) <= clk; input(9) <= shift(0);