It is a more complex example for Series 2 FPGA Boards which demonstrates
This example uses the Default Firmware. A large FIFO is implemented using SDRAM or BRAM, respectively. Input of this FIFO is either the hi-speed input channel of the default Interface or a test pattern generator with variable data rate. Data is written to host using the hi-speed output channel of the Default Interface.
The host software writes the data (in/out mode), reads it back and verifies it. Several tests are performed in order to test flow control, data rates, etc.
Reset is handled through the dedicated reset pin of the Default Interface. Furthermore two GPIOs are used to select the data source:
|0:0||Hi-speed input channel of the Default Interface|
|0:1||48 MByte/s (FX2) or 208 MByte/s (FX3) test pattern generator|
|1:0||12 MByte/s (Fx2) or 13 MByte/s (FX3) test pattern generator|
|1:1||unused, reserved for testing purposes|
The examples can use the Debug Board to output some information (its usage is not required).
The HDL sources are divided into 4 modules:
ezusb_io.v: Part of the Default interface. Implements high-speed communication.
ezusb_gpio.v: Part of the Default interface. Implements GPIO's for mode selection.
dram_fifo.v: Implements a large FIFO from all SDRAM, if available
bram_fifo.v: Implements a FIFO from all BRAM, if no SDRAM is available
memfifo.vhdl: The top level module glues everything together.
Modules 1., 2., 3a. and 3b. are re-usable. Their instantiation is demonstrated in the top level module which is available in Verilog and VHDL. Descriptions can be found on the Default interface page and below.
This module implements a FIFO which is built using SDRAM (dram_fifo) or Block RAM (BRAM, bram_fifo).
Three variants exist in the SDK
|FPGA type||Memory type||Module||FPGA Board|
|Artix 7||DDR3 SDRAM||dram_fifo|| USB-FPGA Module 2.13
USB-FPGA Module 2.14
USB-FPGA Module 2.18
|Spartan 6||DDR SDRAM||dram_fifo||USB-FPGA Module 2.04|
|all||Block RAM||bram_fifo|| USB-FPGA Module 2.16
USB-FPGA Module 2.01
The FIFO interface is not 100% compatible, but the protocol is always the same: it's a FWFT (forst word falls through) FIFO as described in Xilinx UG473. The common part of the interface is describes by the following code snippet, the differences are listed below.
module .ram_fifo # ( input reset, // asynchronous reset input // FIFO protocol equal to FWFT FIFO in "7 Series Memory Resources" user guide (ug743) // input interface of the FIFO input [31:0] DI, // input data, 128 bit with Artix 7 + SDRAM, otherwise 32 bit // must be hold while FULL is asserted output FULL, // full flag output reg WRERR, // write error input WRCLK, // write clock input WREN, // write enable // output interface of the FIFO output reg [31:0] DO, // output data, 128 bit with Artix 7 + SDRAM, otherwise 32 bit output reg EMPTY, // empty flag, can be used as data valid indicator output reg RDERR, // read error input RDCLK, // read clock input RDEN // read enable );
DO) is 128 Bit on FPGA Boards with Artix 7 and external RAM, 32 Bit on all other FPGA Boards
FXCLK) and at least one clock output with adjustable parameters (see comments in the examples)