In order to simplify the porting of applications from USB-FPGA Modules 1.15d and 1.15x to USB-FPGA Modules 1.15y the FPGA Boards are designed to be as compatible as possible.
The I/O signals of the EZ-USB FX2 micro controller are shared by all FPGA's. These signals form a bus which is controlled by the FX2 USB controller using chip select (CS) signals. This is depicted in the USB-FPGA Module 1.15y block diagram:
In order to ensure signal quality all clock signals are distributed using the CPLD.
The following checklist contains things that have to be considered for porting the HDL code
The EZ-USB controls the FPGA communication using the CS signals. These signals are implemented in the Firmware Kit of the SDk and can be controlled by the host software. In simplest case only the FPGA board identification macro has to be changed (to “
For more complex applications the following methods, macros and variables are available.
__xdata BYTE select_num; // currently selected FPGA __xdata BYTE prev_select_num; // previously selected FPGA
PRE_FPGA_SELECT is called between deselection and selection of a FPGA. Typically it is used to sore / restore IO states. The following example saves IOC state for previously selected FPGA and restores the IOC state for the newly selected FPGA.
#define[PRE_FPGA_SELECT][PRE_FPGA_SELECT OLD_IOC[prev_select_num] = IOC; IOC = OLD_IOC[select_num]; ]
void select_fpga ( BYTE fn )
can be used to select an FPGA. In particular this method
prev_select_num = select_num; select_num = fn;
The host software API contains two methods for multi-FPGA boards:
Simple examples can be found is the SDK package. A more complex application (which uses the
PRE_FPGA_SELECT macro is BTCMiner.