This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
en:projects:smartlogic [2011/07/12 12:40] – [Short Introduction] 131.174.142.235 | en:projects:smartlogic [2011/07/12 13:31] (current) – [Introduction] 131.174.142.235 | ||
---|---|---|---|
Line 6: | Line 6: | ||
* **[[https:// | * **[[https:// | ||
- | ===== Short Introduction ===== | + | ===== Introduction ===== |
{{: | {{: | ||
Line 17: | Line 17: | ||
* a smart card interface to connect to the pins of the FPGA board | * a smart card interface to connect to the pins of the FPGA board | ||
+ | ===== Example Setup ===== | ||
+ | |||
+ | ==== Trace of Card Balance Read Out (Dutch Chipknip) ==== | ||
+ | {{: | ||
+ | |||
+ | ==== The SmartLogic ==== | ||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | ==== The Generic Reader ==== | ||
+ | {{: |