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High speed configuration

The following ZTEX FPGA Boards support different configuration speeds:

FPGA Board	Low speed (via EP0)	High speed (via bulk Endpoint)
USB-FPGA Modules 1.15	0.6 MByte/s	24 MByte/s (using the CPLD)
USB-FPGA Modules 1.15x	0.6 MByte/s	1.4 MByte/s
USB-FPGA Modules 1.15y	0.6 MByte/s	24 MByte/s (using the CPLD)
USB-FPGA Modules 2.13	0.6 MByte/s	24 MByte/s (using the CPLD)
USB-FPGA Modules 2.16	0.6 MByte/s	24 MByte/s (using the CPLD)

The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature:

EP_CONFIG(<EPNUM>,<IFNUM>,BULK,OUT,512,<BUFNUM>);	 
ENABLE_HS_FPGA_CONF(<EPNUM>);

EP_CONFIG defines an Endpoint where <EPNUM> stands for the Endpoint number (valid values: 2, 4, 6 , 8), <IFNUM> for the interface number (valid values: 0, 1, 2, 3) and <BUFNUM> for the number of buffers (valid values: 2, 3, 4). After the configuration the Endpoint can be used for other purposes.

ENABLE_HS_FPGA_CONF defines the Endpoint which shall be used for the high speed configuration.

A typical example looks like

// Endpoint 2 is used to high speed FPGA configuration
EP_CONFIG(2,0,BULK,OUT,512,2);	 
 
// enables high speed FPGA configuration, use EP 2
ENABLE_HS_FPGA_CONF(2);

If ENABLE_HS_FPGA_CONF is not defined low speed configuration (about 0.6 MByte/s) via Endpoint 0 is used.

Details about the CPLD (including source code) can be found on the products pages of the FPGA Board that support it.