[[High speed FPGA configuration]]
 
Trace: • USB Powering • Compilation • Build and run standalone samples • FWLoader
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en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2012/05/15 18:29] – 84.181.62.168en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2012/05/15 18:29] – 84.181.62.168
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 | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |
 | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15x.e.html|USB-FPGA Modules 1.15x]]  | 0.6 MByte/s  | 1.4 MByte/s  | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15x.e.html|USB-FPGA Modules 1.15x]]  | 0.6 MByte/s  | 1.4 MByte/s  |
-| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html|USB-FPGA Modules 1.15<]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |+| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html|USB-FPGA Modules 1.15y]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |
  
 The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature: The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature:
 
en/ztex_boards/ztex_fpga_boards/high_speed_configuration.txt · Last modified: 2016/11/24 23:30 by stefan
 
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