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--- en:ztex_boards:ztex_fpga_boards:first_steps_with_ise [2010/12/05 20:51] – [Crating a new project] stefan
+++ en:ztex_boards:ztex_fpga_boards:first_steps_with_ise [2016/08/18 07:05] (current) – gelöscht stefan
@@ Line 1: / Line 1: @@
-====== First steps with ISE ======
-This section describes how FPGA bitstreams are generated and how new projects are created.
-===== Generating the Bitstream =====
-This section describes how the bitstream of an example of the SDK is created with Xilinx ISE.
-  - Start the Xilinx ISE
-  - In the menu: 'File' -> 'Open Project' -> select the .xise project file in the 'fpga' sub-directory the the example and click 'Open'
-  - Single-click on the main source file in the source hierarchy field (1) and double click on 'Generate Programming File' in the Processes view (2): \\ {{:en:ztex_boards:ztex_fpga_boards:ise-intro-1-1.png|ISE Intro: Generating the Bitstream 1}}
-  - The Bitstream is stored in a bit file, e.g. ucecho.bit. These files can be uploaded via USB using the [[en:software:fwloader|FWLoader]] utility or using the API (see the [[en:projects:ucecho_fpga#java_host_softwareucechojava|ucecho example]]) or via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] e.g. using the Xilinx Impact tool by clicking on 'Configure Target Device' in the processes view. \\  {{:en:ztex_boards:ztex_fpga_boards:ise-intro-1-2.png|ISE Intro: Generating the Bitstream 2}}
-===== Crating a new project =====
-This section explain how an new project is created
-**1.** In the ISE menu: 'File' -> 'New Project' \\
-**2.** Enter a project name (e.g. myProject) and the location of the new project: \\
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-1.png|ISE Intro: Creating a new project 1}}\\
-**3.** Select the device settings from the following table below and choose the Simulator / Language (usually "Modelsim-SE VHDL" or "Modelsim-SE Verilog")
-^ USB-FPGA Module ^ Family ^ Device ^ Package ^ Speed ^
-| 1.2 | Spartan 3 | XC3S400  | TQ144  | -4 (or -5 for deluxe variant)  |
-| 1.11a | Spartan 6 | XC6SLX9  | FTG256  | -2  |
-| 1.11b | Spartan 6 | XC6SLX16  | FTG256  | -2  |
-| 1.11c | Spartan 6 | XC6SLX25  | FTG256  | -2  or -3 |
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-2.png|ISE Intro: Creating a new project 2}}\\
-**4.** Create new sources if desired. Usually it is more comfortable to use sources form another project as starting point. This can be done in the next dialog box. (step 5.)\\
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-3.png|ISE Intro: Creating a new project 3}}\\
-**5.** Add existing sources here. If you use sources form another project (as starting point) check the 'Copy to Project' boxes.\\
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-4.png|ISE Intro: Creating a new project 4}}\\
-**6.** Verify the summary and click 'FINISH'.\\
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-5.png|ISE Intro: Creating a new project 5}}\\
-**7.** The new project is created. The sources can be opened by double-clicking on it.\\
-{{:en:ztex_boards:ztex_fpga_boards:ise-intro-2-6.png|ISE Intro: Creating a new project 6}}
-===== Examples =====
-The [[en:software:package_contents|SDK package]] contains several more or less sophisticated examples which can be used as
-starting point for own applications.
-===== VHDL tutorials =====
-There are many VHDL tutorials available in the Internet. One of them (which is much more than just a tutorial) is
-[[http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html|VHDL Tutorial from Jan van der Spiegel]].
-Other ones can be found using [[http://www.google.com/search?q=vhdl+tutorial|Goolge]].
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