Flash access from FPGA

Flash memory of ZTEX Series 2 FPGA boards can be accessed from the USB controller and from FPGA. Since release 20231030, the SDK contains a framework which avoids concurrent accesses to Flash.

This page describes the different scenarios.

Whether the Flash can be accessed by the USB controller while the FPGA is configured is controlled by a Flag in the configuration memory. Setting this flag to 0 by calling

FWLoader -ff 0 -ru

tells the firmware that the FPGA does not access Flash. Thus, the Flash can be accessed by the USB controller while FPGA is configured. This is the default behavior for FX3 based boards. (Changing the flag takes effect after next reboot. This is enforced using the FWLoader parameter -ru).

FWLoader -ff 1 -ru

tells the firmware that FPGA may access Flash memory. Thus, the Flash can not be accessed while FPGA is configured. This is the default behavior for FX2 based boards because on these boards the Flash access from FPGA is always enabled. On FX3 based boards this access is controlled by a CPLD, i.e. this setting also hands over the Flash access to FPGA.

In the firmware, the flash access is controlled using the function pointers flash_claim and flash_release, see the comments in the source code for details. There are several options to coordinate the Flash access:

1. If FPGA does not access Flash: Do nothing, i.e. do not overwrite the function pointers.
2. Copy the behavior from Default Firmware by copying the functions flash_claim2 and flash_release2 and overwriting flash_claim and flash_release with them
3. Implement your own handshaking algorithm in order to coordinate which component can access the Flash by overwriting 'flash_claim and flash_release''