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Standalone applications

In order to implement standalone applications the Firmware has to be uploaded to EEPROM and the Bitstream has to be written to Flash memory. At power-on the USB controller boots the Firmware from EEPROM and the Firmware configures the FPGA using a Bitstream stored in Flash.

The standalone functionality is enabled by two macros in the Firmware source:

ENABLE_FLASH;
ENABLE_FLASH_BITSTREAM;

The first macro enables flash support and the second one enables automatic FPGA configuration if the Firmware finds a Bitstream in Flash memory at start-up. (On Series 2 FPGA Boards ENABLE_FLASH; is optional but omitting it disables Flash access through firmware.)

There are several ways to upload the Bitstream to the Flash memory:

Default firmware / Standalone example

The SDK contains either a default firmware (which is also factory installed on Series 2 FPGA Boards) or a standalone examples for each ZTEX FPGA board that support Flash. These sources define an “empty” Firmware with standalone capabilities, e.g.:

#include[ztex-conf.h]	    // Loads the configuration macros, see ztex-conf.h for the available macros
#include[ztex-utils.h]	    // include basic functions and variables
 
// selects the target FPGA Board
IDENTITY_UFM_1_11(10.12.0.0,0);	 
 
// this product string can also used for identification by the host software
#define[PRODUCT_STRING]["Standalone firmware"]
 
// enable Flash support
ENABLE_FLASH;
ENABLE_FLASH_BITSTREAM;
 
#include[ztex.h]
 
void main(void)	
{
    init_USB();			// init everything
 
    while (1) {	}		//  twiddle thumbs
}

Supported FPGA Boards

The SDK supports standalone functionality for all ZTEX FPGA Boards with Flash memory, in particular:

FPGA Board Flash type Configuration speed Indirect programming
USB-FPGA Module 1.11 microSD 0.17 MByte/s No
USB-FPGA Module 1.15 microSD up to 2.5 MByte/s No
USB-FPGA Module 2.16 SPI up to 16.5 MByte/s Yes
USB-FPGA Module 2.14 SPI up to 12.5 MByte/s No
USB-FPGA Module 2.13 SPI up to 16.5 MByte/s Yes
USB-FPGA Module 2.04 SPI up to 6.5 MByte/s Yes
USB-FPGA Module 2.01 SPI up to 6.5 MByte/s Yes

Hints for Vivado

With the default bitstream settings of Vivado configuration from SPI Flash may not work. The required setting can be found in the constraints file constraints/usb-fpga-2.xdc of the SDK

set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]  
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]  ;# (optional)
 
en/ztex_boards/ztex_fpga_boards/standalone.1464164795.txt.gz · Last modified: 2016/05/25 08:26 by stefan
 
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