[[Running JOP (Java Optimized Processor) on a ZTEX FPGA Board]]
 
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en:projects:jop [2011/07/05 23:37] – 109.230.136.10en:projects:jop [2011/07/18 13:19] – trygvis
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-[[http://www.jopdesign.com/|JOP - Java Optimized Processor]]+===== Running JOP (Java Optimized Processor) on a ZTEX FPGA Board =====
  
-> JOP is one way to use a configurable Java processor in small embedded real-time systems. It shall help to increase the acceptance of Java for these systems.+[[http://www.jopdesign.com/|JOP - Java Optimized Processor]] - is one way to use a configurable Java processor in small embedded real-time systems. It shall help to increase the acceptance of Java for these systems.
  
-Now JOP processor works on ZTEX boards. With DDR SDRAM support (but 16Mb, yet). FPGA is only used by 23% so you can make multiple cores in CMP JOP+This project explains how a JOP processor can be implemented on a [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|ZTEX USB-FPGA Module 1.11c]] with Spartan6 LX25 FPGA. Currently only 16MB the DDR RAM (of 64MB) are supported. The FPGA utilization is about 23% which allows to build multiple cores in CMP JOP.
  
 ===== Download the fresh Source ===== ===== Download the fresh Source =====
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 <code>make jopser</code> <code>make jopser</code>
 +
 +By default the JOP build is set up to use the quartus tools so the make command will fail with ''quartus_map: Command not found''. This is ok.
 +
 +===== Open the project in ISE =====
 +
 +Open the file ''xilinx/ztex/ise_13/ise_13.xise''. Once the project has loaded you will get a dialog asking you for the path for a few files. These files will be generate in the next step so dismiss the dialog for now.
 +
 +The sources for the MIG has to be added to the project. Add the file ''xilinx/ztex/mig_37/mig_37.xco'' and the icon for the u_mig37 "file" should change from a question mark to a light bulb. TODO: Why is this needed? -Trygve
  
 ===== Create the Spartan-6 DDR memory interface ===== ===== Create the Spartan-6 DDR memory interface =====
  
-Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file xilinx/ztex/mig_37/mig_37.xco for Coregen+First the project has to be configure to generate VHDL instead of Verilog. Open the Design Properties dialog (Project -> Design Properties) and make sure "Preferred Language" is "VHDL" instead of "Verilog". TODO: It should be possible to check in this change to git - trygve 
 + 
 +Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file ''xilinx/ztex/mig_37/mig_37.xco'' for Coregen
  
   * Component Name: mig_37   * Component Name: mig_37
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   * Memory Address Mapping Selection: Row, Bank, Column   * Memory Address Mapping Selection: Row, Bank, Column
  
-Once the controller is generated copy all the vhdl files from the user_design/rtl directory to xilinx/ztex/mig_37 directory and apply patch:+Once the controller is generated copy all the VHDL files from the ''xilinx/ztex/mig_37/mig_37/user_design/rtl/*.vhd'' directory to ''xilinx/ztex/mig_37'' directory and apply patch:
  
 <code>patch < memc3_infrastructure.patch</code> <code>patch < memc3_infrastructure.patch</code>
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 Run make in directory xilinx/ztex or load project xilinx/ztex/ise_13/ise_13.xise to [[en:ztex_boards:ztex_fpga_boards:first_steps_with_ise|ISE]] Run make in directory xilinx/ztex or load project xilinx/ztex/ise_13/ise_13.xise to [[en:ztex_boards:ztex_fpga_boards:first_steps_with_ise|ISE]]
 +
 +===== EZ-USB FX2 Firmware =====
 +
 +No special firmware is required in order to run JOP. The [[en:ztex_boards:ztex_fpga_boards:standalone|standalone firmware]]
 +from the ZTEX SDK can be used as dummy firmware and to allow Bitstream uploading via USB.
  
 ===== Load bitstream ===== ===== Load bitstream =====
  
-Use [[en:software:FWLoader]] or Xilinx impact+The bitstream can be uploaded via USB using [[en:software:FWLoader]] or via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] 
 +using Xilinx Impact.
  
 ===== Connect serial console ===== ===== Connect serial console =====
  
-Connect serial cable to line "A"+In order to verify the functionality of the JOP a serial adapter cable need to be connected to the FPGA Board. 
 + 
 +By default, the serial port is connected to the following pins: 
 + 
 +^ Name  ^ FPGA ball  ^  Pin of the FPGA Board  ^ Pin at the Experimental board  ^ 
 +| TX  | C13  | A13  | A13  | 
 +| RX  | A14  | A12  | A12  |
  
-  * tx PIN 12 +If other pins are preferred, lines around line 11 nedd to be changed.
-  * rx PIN 13+
  
 ===== Compiling and Downloading the Java Application ===== ===== Compiling and Downloading the Java Application =====
  
-From root dir of jop make:+From root directory of jop make:
  
 <code>make japp -e P1=bench P2=jbe P3=DoAll</code> <code>make japp -e P1=bench P2=jbe P3=DoAll</code>
 
en/projects/jop.txt · Last modified: 2017/08/22 07:25 by 188.162.65.65
 
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