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en:projects:jop [2011/07/06 11:15] 84.181.78.148en:projects:jop [2017/08/22 07:25] (current) – Change sources url 188.162.65.65
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-====== Running JOP (Java Optimized Processor) on a ZTEX FPGA Board ======+===== Running JOP (Java Optimized Processor) on a ZTEX FPGA Board =====
  
 [[http://www.jopdesign.com/|JOP - Java Optimized Processor]] - is one way to use a configurable Java processor in small embedded real-time systems. It shall help to increase the acceptance of Java for these systems. [[http://www.jopdesign.com/|JOP - Java Optimized Processor]] - is one way to use a configurable Java processor in small embedded real-time systems. It shall help to increase the acceptance of Java for these systems.
  
-This project explains how a JOP processor can be implemented on a [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|ZTEX USB-FPGA Module 1.11c]] with Spartan6 LX25 FPGA. Currently only 16MB the DDR RAM (of 64MB) are supported. The FPGA utilization is about 23% which allows to build  +This project explains how a JOP processor can be implemented on a [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|ZTEX USB-FPGA Module 1.11c]] with Spartan6 LX25 FPGA. Currently only 16MB the DDR RAM (of 64MB) are supported. The FPGA utilization is about 23% which allows to build multiple cores in CMP JOP.
-multiple cores in CMP JOP.+
  
 ===== Download the fresh Source ===== ===== Download the fresh Source =====
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 The latest version can be obtained from with following Git command:  The latest version can be obtained from with following Git command: 
  
-<code>git clone git://www.soc.tuwien.ac.at/jop.git</code>+<code>git clone https://github.com/jop-devel/jop</code>
  
 Create the needed directories with:  Create the needed directories with: 
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 <code>make jopser</code> <code>make jopser</code>
 +
 +By default the JOP build is set up to use the quartus tools so the make command will fail with ''quartus_map: Command not found''. This is ok.
 +
 +===== Open the project in ISE =====
 +
 +Open the file ''xilinx/ztex/ise_13/ise_13.xise''. Once the project has loaded you will get a dialog asking you for the path for a few files. These files will be generate in the next step so dismiss the dialog for now.
 +
 +The sources for the MIG has to be added to the project. Add the file ''xilinx/ztex/mig_37/mig_37.xco'' and the icon for the u_mig37 "file" should change from a question mark to a light bulb. TODO: Why is this needed? -Trygve
  
 ===== Create the Spartan-6 DDR memory interface ===== ===== Create the Spartan-6 DDR memory interface =====
  
-Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file xilinx/ztex/mig_37/mig_37.xco for Coregen+First the project has to be configure to generate VHDL instead of Verilog. Open the Design Properties dialog (Project -> Design Properties) and make sure "Preferred Language" is "VHDL" instead of "Verilog". TODO: It should be possible to check in this change to git - trygve 
 + 
 +Use Coregen/MIG 3.7 (or 3.61 for ISE 12.4) to create the controller. You may use file ''xilinx/ztex/mig_37/mig_37.xco'' for Coregen
  
   * Component Name: mig_37   * Component Name: mig_37
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   * Memory Address Mapping Selection: Row, Bank, Column   * Memory Address Mapping Selection: Row, Bank, Column
  
-Once the controller is generated copy all the VHDL files from the user_design/rtl directory to xilinx/ztex/mig_37 directory and apply patch:+Once the controller is generated copy all the VHDL files from the ''xilinx/ztex/mig_37/mig_37/user_design/rtl/*.vhd'' directory to ''xilinx/ztex/mig_37'' directory and apply patch:
  
 <code>patch < memc3_infrastructure.patch</code> <code>patch < memc3_infrastructure.patch</code>
 
en/projects/jop.txt · Last modified: 2017/08/22 07:25 by 188.162.65.65
 
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