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en:projects:la [2011/07/30 16:53] – strijar | en:projects:la [2011/08/04 13:01] – Analizer => Analyzer trygvis | ||
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- | ===== Logic Analizer | + | ===== Logic Analyzer |
The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. | The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. | ||
- | This is a slightly modified version of [[http:// | + | This is a slightly modified version of [[http:// |
+ | ===== Download and build ===== | ||
+ | |||
+ | * download [[http:// | ||
+ | * unpack it | ||
+ | |||
+ | For build do: | ||
+ | |||
+ | make | ||
+ | |||
+ | ===== EZ-USB FX2 Firmware ===== | ||
+ | |||
+ | No special firmware is required in order to run LA. The [[en: | ||
+ | |||
+ | ===== Load bitstream ===== | ||
+ | |||
+ | The bitstream can be uploaded via USB using [[en: | ||
+ | |||
+ | ===== Connect serial console ===== | ||
+ | |||
+ | For work with LA a serial adapter cable need to be connected to the FPGA Board. | ||
+ | |||
+ | By default, the serial port is connected to the following pins: | ||
+ | |||
+ | ^ Name ^ FPGA ball ^ Pin of the FPGA Board ^ Pin at the Experimental board ^ | ||
+ | | TX | C13 | A13 | A13 | | ||
+ | | RX | A14 | A12 | A12 | | ||
+ | |||
+ | If other pins are preferred, lines around line 6 need to be changed. Default baud rate is **921600** specified in the file top.vhd | ||
+ | |||
+ | ===== Client ===== | ||
+ | |||
+ | Best to use an [[http:// | ||
+ | |||
+ | [[Client screenshot|{{http:// | ||
+ | |||
+ | Here you see the test signals are generated in top.vhd: | ||
+ | |||
+ | process (clock) begin | ||
+ | if rising_edge(clock) then | ||
+ | if rst = ' | ||
+ | counter <= (others => ' | ||
+ | shift <= " | ||
+ | else | ||
+ | counter <= counter + 1; | ||
+ | shift <= shift(6 downto 0) & shift(7); | ||
+ | end if; | ||
+ | end if; | ||
+ | end process; | ||
+ | | ||
+ | input(7 downto 0) <= counter; | ||
+ | input(8) <= clk; | ||
+ | input(9) <= shift(0); |