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--- en:projects:la [2011/07/30 17:12] – strijar
+++ en:projects:la [2011/07/30 17:21] – [Client] strijar
@@ Line 42: / Line 42: @@
 Here you see the test signals are generated in top.vhd:
-  * [0:7] 8-bit counter
+  process (clock) begin
-  * [8] clock
+    if rising_edge(clock) then
-  * [9] simple shift data
+      if rst = '1' then
+        counter <= (others => '0');
+        shift <= "10110000";
+      else
+        counter <= counter + 1;
+        shift <= shift(6 downto 0) & shift(7);
+      end if;
+    end if;
+  end process;
+  input(7 downto 0) <= counter;
+  input(8) <= clk;
+  input(9) <= shift(0);