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en:projects:la [2011/07/30 17:12] – strijar | en:projects:la [2011/08/04 13:01] – Analizer => Analyzer trygvis | ||
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- | ===== Logic Analizer | + | ===== Logic Analyzer |
The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. | The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. | ||
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Here you see the test signals are generated in top.vhd: | Here you see the test signals are generated in top.vhd: | ||
- | | + | |
- | | + | if rising_edge(clock) then |
- | | + | if rst = ' |
+ | counter <= (others => '0'); | ||
+ | shift <= " | ||
+ | else | ||
+ | counter <= counter + 1; | ||
+ | shift <= shift(6 downto 0) & shift(7); | ||
+ | end if; | ||
+ | end if; | ||
+ | end process; | ||
+ | |||
+ | input(7 downto 0) <= counter; | ||
+ | | ||
+ | |