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en:projects:la [2011/07/30 17:12] strijaren:projects:la [2017/09/19 10:29] (current) – Change client url 188.162.64.48
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-===== Logic Analizer =====+===== Logic Analyzer =====
  
 The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. The Logic Analyzer supports 32 channels with 6K sample memory. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis.
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 ===== Client ===== ===== Client =====
  
-Best to use an [[http://ols.lxtreme.nl/|alternate client.]] Download it and unpack. After start select "Capture" in menu, then "Begin capture". Or press <Ctrl-B>. Select your serial port and baud rate, then press "Capture" button.+Best to use an [[https://lxtreme.nl/projects/ols/|alternate client.]] Download it and unpack. After start select "Capture" in menu, then "Begin capture". Or press <Ctrl-B>. Select your serial port and baud rate, then press "Capture" button.
  
 [[Client screenshot|{{http://www.strijar.ru/ztex/la_screen.png}}]] [[Client screenshot|{{http://www.strijar.ru/ztex/la_screen.png}}]]
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 Here you see the test signals are generated in top.vhd: Here you see the test signals are generated in top.vhd:
  
-  * [0:7] 8-bit counter +  process (clock) begin 
-  * [8] clock +    if rising_edge(clock) then 
-  * [9] simple shift data +      if rst = '1' then 
 +        counter <= (others => '0'); 
 +        shift <= "10110000"; 
 +      else 
 +        counter <= counter + 1; 
 +        shift <= shift(6 downto 0) & shift(7); 
 +      end if; 
 +    end if; 
 +  end process; 
 +   
 +  input(7 downto 0) <= counter; 
 +  input(8) <= clk; 
 +  input(9) <= shift(0);
 
en/projects/la.txt · Last modified: 2017/09/19 10:29 by 188.162.64.48
 
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