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| en:projects:leon3 [2011/08/20 11:31] – [LEON3 SPARC processor] strijar | en:projects:leon3 [2011/08/20 11:32] – [LEON3 SPARC processor] strijar |
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| The [[http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53|LEON3]] is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. | The [[http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53|LEON3]] is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. |
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| This project explains how a LEON3 processor can be implemented on: | This project explains how a LEON3 processor can be implemented on a ZTEX Modules: |
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| ^ Module ^ FPGA ^ CPU cores ^ MMU ^ FPU ^ Utilization ^ Linux ^ | ^ Module ^ FPGA ^ CPU cores ^ MMU ^ FPU ^ Utilization ^ Linux ^ |
