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--- en:projects:smartlogic [2011/07/12 12:37] – [Short Introduction] 131.174.142.235
+++ en:projects:smartlogic [2011/07/12 13:31] (current) – [Introduction] 131.174.142.235
@@ Line 6: / Line 6: @@
   * **[[https://code.google.com/p/smartlogictool/|SmartLogic source code (Google Code)]]**
-===== Short Introduction =====
+===== Introduction =====
 {{:en:projects:setup_fpgacard_web.png|SmartLogic Setup}}
 This project uses
-  * the ZTEX-USB-FPGA 1.2 and FPGA powerboard
+  * the [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.2.e.html|ZTEX USB-FPGA-Module 1.2]]
+  * the [[http://www.ztex.de/usb-fpga-1/pwr-1.0.e.html|Power Supply Module]] for USB-FPGA boards
   * the [[http://scuba.sourceforge.net/|SCUBA smart card project]] (included in the source)
+  * a generic smart card reader
   * a smart card interface to connect to the pins of the FPGA board
+===== Example Setup =====
+==== Trace of Card Balance Read Out (Dutch Chipknip) ====
+{{:en:projects:smartlogic:trace_chipknip_small.gif|Trace of the Dutch Chipknip}}
+==== The SmartLogic ====
+{{:en:projects:smartlogic:smartlogic_01.png|}}
+{{:en:projects:smartlogic:smartlogic_02.png|}}
+==== The Generic Reader ====
+{{:en:projects:smartlogic:reader.png|}}