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--- en:software:default_firmware [2016/09/11 10:46] – [Default Firmware] stefan
+++ en:software:default_firmware [2017/10/10 13:27] – [ezusb_gpio.v] 87.177.180.166
@@ Line 36: / Line 36: @@
   * shared EZ-USB <-> FPGA bandwidth: 96 MByte/s (FX2) or 208 MByte/s (FX3)
   * usable host <-> FPGA bandwidth: 30..35 MByte/s (USB 2.0) or 200..207 MByte/s (FX3 in USB 3.0 mode)
-  * Automatic committing 'PKTEND' after timeout
+  * short packet support using 'PKTEND'
 The interface is compatible for all FPGA Boards and listed below. A brief description is given in the comments. The hardware pins are omitted because they depend from the EZ-USB variant and are directly connected to the interface of the top level module. In order to learn more about the usage please take a look into the top level module of the [[en:ztex_boards:ztex_fpga_boards:memfifo:memfifo|memfifo examle]].
@@ Line 71: / Line 71: @@
     );
 </code>
+==== ezusb_lsi.v ====
+This module is intended for low speed communication, such as transfer of configuration data.It has an easy-to-use SRAM like interface and is used in the ucecho example. Particular features are:
+  * SRAM-like interface
+  * 1 read port, 1 write port
+  * 256 32 Bit registers
+The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments.
+<code verilog>
+// all directions are seen from FPGA
+module ezusb_lsi (
+	// control signals
+	input clk,			// at least 24MHz
+	input reset_in,			// high-active asynchronous reset
+	output reg reset,	        // synchronous reset output
+	// hardware pins
+        // ...
+	// user interface
+	output reg [7:0] in_addr,	// input address
+	output reg [31:0] in_data,	// input data
+	output reg in_strobe,     	// 1 indicates new data received (1 for one cycle)
+	output reg in_valid,    	// 1 if data is valid
+	output reg [7:0] out_addr,      // output address
+	input [31:0] out_data,          // output data
+	output reg out_strobe	        // 1 indicates new data request (1 for one cycle)
+    );
+</code>
+==== ezusb_gpio.v ====
+The default interface implements 4 freely usable and independent bidirectional GPIO pins. It is used in the [[en:ztex_boards:ztex_fpga_boards:memfifo:memfifo|memfifo examle]]. The user interface is independent from FPGA board and listed an described (see the comments) below. Just the hardware pins differ (omitted below).
+<code verilog>
+// all directions are seen from FPGA
+module ezusb_gpio (
+	// control signals
+	input clk,			// system clock, minimum frequency is 24 MHz
+	// hardware pins
+        // ...
+	// interface
+	output reg [3:0] in,	        // inputs
+	input [3:0] out			// wired-OR outputs: GPIO's not used for output must be 0
+    );
+</code>
+===== Device Identification =====
+Default Firmware has several configurable properties which can be used to identify devices, e.g. if several FPGA Boards are running on the same host.
+All of them can be set using ''[[en:software:fwloader|FWLoader]]''.
+^ Property  ^  ''FWLoader'' parameter  ^
+| USB vendor ID (must be purchased from USB IF) and product ID  | ''-su <VID> <PID>''  |
+| Product name  | ''-sp <string> ''  |
+| Custom serial number (up to 10 characters)  | ''-ss <sn string>''  |
+| Default unique serial number stored in MAC EEPROM  | ''-ss 0000000000''  |
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