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en:software:default_firmware [2016/09/11 10:46] – [Default Firmware] stefan | en:software:default_firmware [2018/09/12 13:54] – [ezusb_io.v] 83.173.241.10 | ||
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==== ezusb_io.v ==== | ==== ezusb_io.v ==== | ||
- | This module implements | + | This module implements the high-speed communication for both directions using the EZ-USB Slave FIFO interface (FX2) or GPIF2 (FX3). |
It provides the following features: | It provides the following features: | ||
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* shared EZ-USB <-> FPGA bandwidth: 96 MByte/s (FX2) or 208 MByte/s (FX3) | * shared EZ-USB <-> FPGA bandwidth: 96 MByte/s (FX2) or 208 MByte/s (FX3) | ||
* usable host <-> FPGA bandwidth: 30..35 MByte/s (USB 2.0) or 200..207 MByte/s (FX3 in USB 3.0 mode) | * usable host <-> FPGA bandwidth: 30..35 MByte/s (USB 2.0) or 200..207 MByte/s (FX3 in USB 3.0 mode) | ||
- | * Automatic committing | + | * short packet support using ' |
The interface is compatible for all FPGA Boards and listed below. A brief description is given in the comments. The hardware pins are omitted because they depend from the EZ-USB variant and are directly connected to the interface of the top level module. In order to learn more about the usage please take a look into the top level module of the [[en: | The interface is compatible for all FPGA Boards and listed below. A brief description is given in the comments. The hardware pins are omitted because they depend from the EZ-USB variant and are directly connected to the interface of the top level module. In order to learn more about the usage please take a look into the top level module of the [[en: | ||
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); | ); | ||
</ | </ | ||
+ | |||
+ | ==== ezusb_lsi.v ==== | ||
+ | |||
+ | This module is intended for low speed communication, | ||
+ | |||
+ | * SRAM-like interface | ||
+ | * 1 read port, 1 write port | ||
+ | * 256 32 Bit registers | ||
+ | |||
+ | The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments. | ||
+ | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
+ | module ezusb_lsi ( | ||
+ | // control signals | ||
+ | input clk, // at least 24MHz | ||
+ | input reset_in, | ||
+ | output reg reset, | ||
+ | // hardware pins | ||
+ | // ... | ||
+ | // user interface | ||
+ | output reg [7:0] in_addr, // input address | ||
+ | output reg [31:0] in_data, // input data | ||
+ | output reg in_strobe, | ||
+ | output reg in_valid, | ||
+ | output reg [7:0] out_addr, | ||
+ | input [31:0] out_data, | ||
+ | output reg out_strobe | ||
+ | ); | ||
+ | </ | ||
+ | |||
+ | ==== ezusb_gpio.v ==== | ||
+ | The default interface implements 4 freely usable and independent bidirectional GPIO pins. It is used in the [[en: | ||
+ | |||
+ | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
+ | module ezusb_gpio ( | ||
+ | // control signals | ||
+ | input clk, // system clock, minimum frequency is 24 MHz | ||
+ | // hardware pins | ||
+ | // ... | ||
+ | // interface | ||
+ | output reg [3:0] in, // inputs | ||
+ | input [3:0] out // wired-OR outputs: GPIO's not used for output must be 0 | ||
+ | ); | ||
+ | </ | ||
+ | |||
+ | ===== Device Identification ===== | ||
+ | Default Firmware has several configurable properties which can be used to identify devices, e.g. if several FPGA Boards are running on the same host. | ||
+ | All of them can be set using '' | ||
+ | ^ Property | ||
+ | | USB vendor ID (must be purchased from USB IF) and product ID | '' | ||
+ | | Product name | '' | ||
+ | | Custom serial number (up to 10 characters) | ||
+ | | Default unique serial number stored in MAC EEPROM | ||
+ | |||
{{indexmenu_n> | {{indexmenu_n> |