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--- en:software:default_firmware [2017/03/22 21:54] – stefan
+++ en:software:default_firmware [2017/10/10 13:15] – [ezusb_io.v] 87.177.180.166
@@ Line 71: / Line 71: @@
     );
 </code>
+==== ezusb_lsi.v ====
+This module is intended for low speed communication, such as transfer of configuration data.It has an easy-to-use SRAM like interface and is used in the ucecho example. Particular features are:
+  * SRAM-like interface
+  * 1 read port, 1 write port
+  * 256 32 Bit registers
+The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments.
+<code verilog>
+module ezusb_lsi (
+	// control signals
+	input clk,			// at least 24MHz
+	input reset_in,			// high-active asynchronous reset
+	output reg reset,	        // synchronous reset output
+	// hardware pins
+        // ...
+	// user interface
+	output reg [7:0] in_addr,	// input address
+	output reg [31:0] in_data,	// input data
+	output reg in_strobe,     	// 1 indicates new data received (1 for one cycle)
+	output reg in_valid,    	// 1 if data is valid
+	output reg [7:0] out_addr,      // output address
+	input [31:0] out_data,          // output data
+	output reg out_strobe	        // 1 indicates new data request (1 for one cycle)
+    );
+</code>
 ===== Device Identification =====