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en:software:default_firmware [2017/10/10 13:15] – [ezusb_io.v] 87.177.180.166 | en:software:default_firmware [2018/09/12 13:54] – [ezusb_io.v] 83.173.241.10 | ||
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==== ezusb_io.v ==== | ==== ezusb_io.v ==== | ||
- | This module implements | + | This module implements the high-speed communication for both directions using the EZ-USB Slave FIFO interface (FX2) or GPIF2 (FX3). |
It provides the following features: | It provides the following features: | ||
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The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments. | The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments. | ||
<code verilog> | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
module ezusb_lsi ( | module ezusb_lsi ( | ||
// control signals | // control signals | ||
Line 99: | Line 100: | ||
); | ); | ||
</ | </ | ||
+ | |||
+ | ==== ezusb_gpio.v ==== | ||
+ | The default interface implements 4 freely usable and independent bidirectional GPIO pins. It is used in the [[en: | ||
+ | |||
+ | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
+ | module ezusb_gpio ( | ||
+ | // control signals | ||
+ | input clk, // system clock, minimum frequency is 24 MHz | ||
+ | // hardware pins | ||
+ | // ... | ||
+ | // interface | ||
+ | output reg [3:0] in, // inputs | ||
+ | input [3:0] out // wired-OR outputs: GPIO's not used for output must be 0 | ||
+ | ); | ||
+ | </ | ||
===== Device Identification ===== | ===== Device Identification ===== |