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en:software:default_firmware [2017/10/10 13:15] – [ezusb_io.v] 87.177.180.166 | en:software:default_firmware [2023/10/30 20:26] (current) – [HDL Modules] stefan | ||
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^ Module Name ^ Description | ^ Module Name ^ Description | ||
- | | '' | + | | '' |
| '' | | '' | ||
- | | '' | + | | '' |
==== ezusb_io.v ==== | ==== ezusb_io.v ==== | ||
- | This module implements | + | This module implements the high-speed communication for both directions using the EZ-USB Slave FIFO interface (FX2) or GPIF2 (FX3). |
It provides the following features: | It provides the following features: | ||
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<code verilog> | <code verilog> | ||
- | module ezusb_io | + | module ezusb_io ( |
- | parameter OUTEP = 2, // FX2 only: Endpoint for FPGA -> EZ-USB transfers | + | output ifclk, |
- | parameter INEP = 6 , // FX2 only: Endpoint for EZ-USB -> FPGA transfers | + | |
- | parameter TARGET = "" | + | |
- | ) ( | + | |
- | output ifclk, | + | |
- | // this is the clock for the user logic | + | |
input reset, | input reset, | ||
- | output reset_out, | + | output reset_out, // synchronous reset output |
- | + | | |
- | // FPGA pins that are connected directly to EZ-USB are omitted here | + | |
- | + | inout [15:0] fd, | |
- | // Signals | + | output reg SLWR, SLRD, |
+ | output reg SLOE, PKTEND, // low active | ||
+ | input EMPTY_FLAG, FULL_FLAG, | ||
+ | // signals | ||
input [15:0] DI, // data written to EZ-USB | input [15:0] DI, // data written to EZ-USB | ||
- | input DI_valid, | + | input DI_valid, |
- | output DI_ready, | + | output DI_ready, |
input DI_enable, | input DI_enable, | ||
- | | + | input pktend_arm, |
+ | // PKTEND is asserted as soon output becomes idle | ||
+ | // recommended procedure for accurate packet transfers: | ||
+ | // * DI_valid goes low after last data of package | ||
+ | // * monitor PKTEND and hold DI_valid until PKTEND is asserted (PKTEND = 0) | ||
+ | | ||
// setting to 0 disables this feature | // setting to 0 disables this feature | ||
- | + | // signals | |
- | // Signals | + | |
output reg [15:0] DO, // data read from EZ-USB | output reg [15:0] DO, // data read from EZ-USB | ||
- | output reg DO_valid, | + | output reg DO_valid, |
- | input DO_ready, | + | input DO_ready, |
- | // DO and DO_valid are hold if DO_ready is 0 | + | |
// set to 0 to disable data reads | // set to 0 to disable data reads | ||
// debug output | // debug output | ||
- | output [3:0] status | + | output [6:0] status |
); | ); | ||
</ | </ | ||
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The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments. | The user-interface is the same for both EZ-USB variants. Only the hardware pins depends on type of FPGA-Board and are omitted here (copy it from the examples). A short description is given in the comments. | ||
<code verilog> | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
module ezusb_lsi ( | module ezusb_lsi ( | ||
// control signals | // control signals | ||
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); | ); | ||
</ | </ | ||
+ | |||
+ | ==== ezusb_gpio.v ==== | ||
+ | The default interface implements 4 freely usable and independent bidirectional GPIO pins. It is used in the [[en: | ||
+ | |||
+ | <code verilog> | ||
+ | // all directions are seen from FPGA | ||
+ | module ezusb_gpio ( | ||
+ | // control signals | ||
+ | input clk, // system clock, minimum frequency is 24 MHz | ||
+ | // hardware pins | ||
+ | // ... | ||
+ | // interface | ||
+ | output reg [3:0] in, // inputs | ||
+ | input [3:0] out // wired-OR outputs: GPIO's not used for output must be 0 | ||
+ | ); | ||
+ | </ | ||
===== Device Identification ===== | ===== Device Identification ===== |