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en:software:default_firmware [2018/09/12 13:54] – [ezusb_io.v] 83.173.241.10en:software:default_firmware [2019/07/05 15:18] (current) – [ezusb_io.v] stefan
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 <code verilog> <code verilog>
-module ezusb_io #( +module ezusb_io ( 
- parameter OUTEP = 2,            // FX2 only: Endpoint for FPGA -> EZ-USB transfers +        output ifclk,
- parameter INEP = 6 ,            // FX2 only: Endpoint for EZ-USB -> FPGA transfers  +
- parameter TARGET = "" // FX2 only: Target FPGA: "A7": Artix 7, "" all others +
-    ) +
-        output ifclk,                   // buffered output of the interface clock +
-                                        // this is the clock for the user logic+
         input reset,                    // asynchronous reset input         input reset,                    // asynchronous reset input
-        output reset_out,  // synchronous reset output +        output reset_out, // synchronous reset output 
-         +        // pins 
-        // FPGA pins that are connected directly to EZ-USB are omitted here +        input ifclk_in, 
- +        inout [15:0] fd, 
- // Signals for FPGA -> EZ-USB transfer. The are controlled by user logic.+ output reg SLWR, SLRD,         // low active 
 + output reg SLOE, PKTEND, // low active 
 + input EMPTY_FLAG, FULL_FLAG, // almost full/empty due to flag latency of several clocks, low active 
 +// signals for FPGA -> EZ-USB transfer
         input [15:0] DI,                // data written to EZ-USB         input [15:0] DI,                // data written to EZ-USB
-        input DI_valid, // 1 indicates valid data; DI and DI_valid must be hold if DI_ready is 0 +        input DI_valid, // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0 
-        output DI_ready,   // 1 if new data are accepted+        output DI_ready,  // 1 if new data are accepted
         input DI_enable, // setting to 0 disables FPGA -> EZ-USB transfers         input DI_enable, // setting to 0 disables FPGA -> EZ-USB transfers
-        input [15:0] pktend_timeout, // timeout in multiples of 65536 clocks before a short packet committed+    input pktend_arm, // 0->1 transition enables the manual PKTEND mechanism: 
 +                                    // PKTEND is asserted as soon output becomes idle 
 +                                    // recommended procedure for accurate packet transfers: 
 +                                    //   * DI_valid goes low after last data of package 
 +                                    //   * monitor PKTEND and hold DI_valid until PKTEND is asserted (PKTEND = 0) 
 +        input [15:0] pktend_timeout, // automatic PKTEN assertion after pktend_timeout*65536 clocks of no output data
     // setting to 0 disables this feature     // setting to 0 disables this feature
-     + // signals for EZ-USB -> FPGA transfer
- // Signals for EZ-USB -> FPGA transfer. They are controlled by user logic.+
         output reg [15:0] DO,           // data read from EZ-USB         output reg [15:0] DO,           // data read from EZ-USB
-        output reg DO_valid, //indicates valid data +        output reg DO_valid, //indicated valid data 
-        input DO_ready, // setting to 1 enables writing new data to DO in next clock +        input DO_ready, // setting to 1 enables writing new data to DO in next clockDO and DO_valid are hold if DO_ready is 0
-                                        // DO and DO_valid are hold if DO_ready is 0+
     // set to 0 to disable data reads      // set to 0 to disable data reads 
         // debug output         // debug output
-        output [3:0] status+        output [6:0] status
     );     );
 </code> </code>
 
en/software/default_firmware.txt · Last modified: 2019/07/05 15:18 by stefan
 
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