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en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2012/05/15 18:29] – 84.181.62.168 | en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2014/07/15 21:46] – stefan |
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====== High speed configuration of USB-FPGA Modules 1.15 ====== | ====== High speed configuration ====== |
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USB-FPGA Modules 1.15, 1.15x and 1.15y support different configuration speeds: | The following ZTEX FPGA Boards support different configuration speeds: |
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^ FPGA Board ^ Low speed (via EP0) ^ High speed (via bulk Endpoint) ^ | ^ FPGA Board ^ Low speed (via EP0) ^ High speed (via bulk Endpoint) ^ |
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | |
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15x.e.html|USB-FPGA Modules 1.15x]] | 0.6 MByte/s | 1.4 MByte/s | | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15x.e.html|USB-FPGA Modules 1.15x]] | 0.6 MByte/s | 1.4 MByte/s | |
| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html|USB-FPGA Modules 1.15<]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html|USB-FPGA Modules 1.15y]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | |
| | [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.13.e.html|USB-FPGA Modules 2.13]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | |
| | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Modules 2.16]] | 0.6 MByte/s | 24 MByte/s (using the CPLD) | |
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The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature: | The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature: |
If ''ENABLE_HS_FPGA_CONF'' is not defined low speed configuration (about 0.6 MByte/s) via Endpoint 0 is used. | If ''ENABLE_HS_FPGA_CONF'' is not defined low speed configuration (about 0.6 MByte/s) via Endpoint 0 is used. |
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Additional details about the CPLD on USb-FPGA Modules 1.15 can be found in the [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html#cpld|Configuration booster CPLD]] section of the products page. | Details about the CPLD (including source code) can be found on the products pages of the FPGA Board that support it. |
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