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--- en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2013/11/25 19:33] – stefan
+++ en:ztex_boards:ztex_fpga_boards:high_speed_configuration [2016/09/11 14:10] – stefan
@@ Line 1: / Line 1: @@
-====== High speed configuration ======
+====== High speed FPGA configuration ======
 The following ZTEX FPGA Boards support different configuration speeds:
 ^ FPGA Board  ^ Low speed (via EP0)  ^ High speed (via bulk Endpoint)  ^
-| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |
+| [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.13.e.html|USB-FPGA Modules 2.13]]  | about 0.6 MByte/s  | up to 24 MByte/s  |
-| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15x.e.html|USB-FPGA Modules 1.15x]]  | 0.6 MByte/s  | 1.4 MByte/s  |
+| [[http://www.ztex.de/usb-fpga-1/usb-fpga-2.14.e.html|USB-FPGA Modules 2.14]]  | about 3 MByte/s  | up to 26 MByte/s  |
-| [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html|USB-FPGA Modules 1.15y]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |
+| [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Modules 2.16]]  | about 0.6 MByte/s  | up to 24 MByte/s  |
-| [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Modules 2.16]]  | 0.6 MByte/s  | 24 MByte/s (using the CPLD) |
-The high speed configuration mode requires an bulk output Endpoint. Two macros must be called in order to enable the feature:
+High speed configuration is supported by [[en:software:default_firmware|Default Firmware]].
+This page describes how to enable enable it in user specific firmware for EZ-USB FX2 and FX3 based FPGA Boards.
+===== Enabling high speed FPGA configuration for EZ-USB FX2 =====
+Two macros must be called in order to enable high speed FPGA configuration:
 <code c>
@@ Line 30: / Line 34: @@
 </code>
-If ''ENABLE_HS_FPGA_CONF'' is not defined low speed configuration (about 0.6 MByte/s) via Endpoint 0 is used.
+===== Enabling high speed FPGA configuration for EZ-USB FX3 =====
+In FX3 firmware there are different methods to enable high speed FPGA configuration, but due to a bug in Cypress SDK it is recommended to create a dedicated
+Endpoint for FPGA configuration. Suggested method is:
-Details about the CPLD (including source code) can be found on the products pages of the FPGA Board that support it.
+<code c>
+// defines endpoint number for FPGA configuration. Modify it if desired.
+#define ZTEX_FPGA_CONF_FAST_EP	6
+// the interface to which the endpoint belongs
+#define ZTEX_FPGA_CONF_FAST_IFACE 1
+// a free PIB socket
+#define ZTEX_FPGA_CONF_FAST_SOCKET CY_U3P_PIB_SOCKET_5
+// endpoint settings
+#define EP_SETUP  \
+    INTERFACE(0, ... ) // application specific endpoint settings \
+        INTERFACE(1,   // configuration endpoint settings \
+	EP_BULK(ZTEX_FPGA_CONF_FAST_EP, OUT, 1, \
+	    DMA(dma_fpga_conf_handle, CY_U3P_DMA_TYPE_AUTO, 1, 2 , ZTEX_FPGA_CONF_FAST_SOCKET, \
+		CB(0,0) \
+	    ) \
+	) \
+    )
+</code>
+In this example interface 1 with Endpoint 6 is created and only used for FPGA configuration. It is also possible to assign the Endpoint to interface 0.  To re-use the enpoint is supported by the ZTEX SDK, Cypress SDK may fail in super speed mode.