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--- en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2010/12/13 18:12] – [Insert the Core into your VHDL code] stefan
+++ en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2011/12/07 19:30] – [Memory clock generation by modification of the MCB PLL] 84.181.93.233
@@ Line 319: / Line 319: @@
 ==== Memory clock generation by modification of the MCB PLL ====
-It is not possible to generate a 200 MHz clock from 48 MHz within the PLL constraints, i.e. only non-standard clocks can be generated with this method. Unfortunately some Spartan 6 FPGA's (namely some early XC6SX25 FPGA's) work unstable with non-standard frequencies. Therefore it cannot be guaranteed that all of the example settings below will work with all USB-FPGA Modules. (All USB-FPGA modules are functionally tested with 200 MHz and the DCM approach described above).
+It is not possible to generate a 200 MHz clock from 48 MHz within the PLL constraints, i.e. only non-standard clocks can be generated with this method.
   - Add the following interconnection to the memory core instantiation: <code>c3_clk0 => CLK,</code>