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en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2011/12/07 19:30] – [Memory clock generation by modification of the MCB PLL] 84.181.93.233en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_11 [2011/12/07 20:28] 84.181.93.233
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   - Select memory part ''MT46V32M16XX-5B-IT'' and make sure that the clock period is 5000 ps: \\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-04.png|USB-FPGA Module 1.11, MIG screen 4}}   - Select memory part ''MT46V32M16XX-5B-IT'' and make sure that the clock period is 5000 ps: \\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-04.png|USB-FPGA Module 1.11, MIG screen 4}}
   - Output Drive Strength should be normal:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-05.png|USB-FPGA Module 1.11, MIG screen 5}}   - Output Drive Strength should be normal:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-05.png|USB-FPGA Module 1.11, MIG screen 5}}
-  - The recommended address mapping scheme is Row-Bank-Column. The memory port setting depend from the application. This are the values for the memtest example:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-06.png|USB-FPGA Module 1.11, MIG screen 6}} +  - The recommended address mapping scheme is Row-Bank-Column. The memory port setting depends from the application. This are the values for the memtest example:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-06.png|USB-FPGA Module 1.11, MIG screen 6}} 
-  - The arbitration settings depend on the application. Usually the Round Robin Algorithm is a good choice:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-07.png|USB-FPGA Module 1.11, MIG screen 7}} +  - The arbitration settings depend on the application. Usually the Round Robin algorithm is a good choice:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-07.png|USB-FPGA Module 1.11, MIG screen 7}} 
-  - Chose SSTL Class II output signal standard, uncalibrated 50 Ohm termination, RZQ on M4 and single-ended system clock:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-08.png|USB-FPGA Module 1.11, MIG screen 8}}+  - Chose SSTL Class II output signal standard, uncalibrated 50 Ohm termination and single-ended system clock:\\ {{:en:ztex_boards:ztex_fpga_boards:mem1_11-08.png|USB-FPGA Module 1.11, MIG screen 8}}
   - Click ''NEXT'' on the following dialog boxes and ''Generate'' on the last screen.   - Click ''NEXT'' on the following dialog boxes and ''Generate'' on the last screen.
  
 
en/ztex_boards/ztex_fpga_boards/memory_tutorial_1_11.txt · Last modified: 2012/02/09 17:32 by stefan
 
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