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en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/01/17 19:55] – [Memory clock generation using a DCM] 84.181.90.8 | en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/02/12 16:48] – [Memory clock generation by modification of the MCB PLL] jappel | ||
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+ | ~~DISCUSSION~~ | ||
+ | With the MIG (Version 3.91) that is generated by more recent versions of the ISE webpack I was unable to get a synthesis without timing errors | ||
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+ | SIM_DEVICE | ||
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+ | Is there a better way to fix this? Or is this the highest speed that can be used with newer MIG versions. | ||
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