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--- en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/02/12 16:48] – [Memory clock generation by modification of the MCB PLL] jappel
+++ en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/02/15 14:00] – [Memory clock generation by modification of the MCB PLL] 84.181.58.125
@@ Line 378: / Line 378: @@
 ~~DISCUSSION~~
-With the MIG (Version 3.91) that is generated by more recent versions of the ISE webpack I was unable to get a synthesis without timing errors  using the recipe above. Only by playing with the phase of clock_3 I got a compliant design synthesized:
-<code>
-         CLKOUT0_DIVIDE     => 2,       -- C_CLKOUT0_DIVIDE,
-         CLKOUT1_DIVIDE     => 2,       -- C_CLKOUT1_DIVIDE,
-         CLKOUT2_DIVIDE     => 16,      -- C_CLKOUT2_DIVIDE,
-         CLKOUT3_DIVIDE     => 8,       -- C_CLKOUT3_DIVIDE,
-         CLKOUT4_DIVIDE     => 1,
-         CLKOUT5_DIVIDE     => 1,
-         CLKOUT0_PHASE      => 0.000,
-         CLKOUT1_PHASE      => 180.000,
-         CLKOUT2_PHASE      => 0.000,
-         CLKOUT3_PHASE      => 360.0/8,   -- 0.000,
-         CLKOUT4_PHASE      => 0.000,
-         CLKOUT5_PHASE      => 0.000,
-         CLKOUT0_DUTY_CYCLE => 0.500,
-         CLKOUT1_DUTY_CYCLE => 0.500,
-         CLKOUT2_DUTY_CYCLE => 0.500,
-         CLKOUT3_DUTY_CYCLE => 0.500,
-         CLKOUT4_DUTY_CYCLE => 0.500,
-         CLKOUT5_DUTY_CYCLE => 0.500,
-	 SIM_DEVICE         => "SPARTAN6",
-         COMPENSATION       => "INTERNAL",
-         DIVCLK_DIVIDE      => 1,       -- C_DIVCLK_DIVIDE,
-         CLKFBOUT_MULT      => 13,      -- C_CLKFBOUT_MULT,
-</code>
-Is there a better way to fix this? Or is this the highest speed that can be used with newer MIG versions.