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--- en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2012/02/12 16:48] – [Memory clock generation by modification of the MCB PLL] jappel
+++ en:ztex_boards:ztex_fpga_boards:memory_tutorial_1_15 [2013/07/05 08:22] – 84.181.52.19
@@ Line 10: / Line 10: @@
   - Choose ''IP Core Generator'' and enter a name for the new Core
   - Select ''Memories & Storage Elements'' -> ''Memory Interface Generators'' -> ''MIG'' and click on ''NEXT'' -> ''FINISH''
-  - Verify the Settings in the first dialog box (USB-FPGA Module 1.15a: xc6slx45-ftg256, speed grade -2; 1.15b: xc6slx75-ftg256; speed grade -3, 1.15d: xc6slx150-ftg256, speed grade -3): \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-01.png|USB-FPGA Module 1.15, MIG screen 1}}
+  - Verify the Settings in the first dialog box (USB-FPGA Module 1.15a: xc6slx45-CSG484, speed grade -2; 1.15b: xc6slx75-CSG484; speed grade -3, 1.15d: xc6slx150-CSG484, speed grade -3): \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-01.png|USB-FPGA Module 1.15, MIG screen 1}}
   - Select "Create Design"\\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-02.png|USB-FPGA Module 1.15, MIG screen 2}}
   - The settings on the next screen can be ignored: \\  {{:en:ztex_boards:ztex_fpga_boards:mem1_15-03.png|USB-FPGA Module 1.15, MIG screen 3}}
@@ Line 378: / Line 378: @@
 ~~DISCUSSION~~
-With the MIG (Version 3.91) that is generated by more recent versions of the ISE webpack I was unable to get a synthesis without timing errors  using the recipe above. Only by playing with the phase of clock_3 I got a compliant design synthesized:
-<code>
-         CLKOUT0_DIVIDE     => 2,       -- C_CLKOUT0_DIVIDE,
-         CLKOUT1_DIVIDE     => 2,       -- C_CLKOUT1_DIVIDE,
-         CLKOUT2_DIVIDE     => 16,      -- C_CLKOUT2_DIVIDE,
-         CLKOUT3_DIVIDE     => 8,       -- C_CLKOUT3_DIVIDE,
-         CLKOUT4_DIVIDE     => 1,
-         CLKOUT5_DIVIDE     => 1,
-         CLKOUT0_PHASE      => 0.000,
-         CLKOUT1_PHASE      => 180.000,
-         CLKOUT2_PHASE      => 0.000,
-         CLKOUT3_PHASE      => 360.0/8,   -- 0.000,
-         CLKOUT4_PHASE      => 0.000,
-         CLKOUT5_PHASE      => 0.000,
-         CLKOUT0_DUTY_CYCLE => 0.500,
-         CLKOUT1_DUTY_CYCLE => 0.500,
-         CLKOUT2_DUTY_CYCLE => 0.500,
-         CLKOUT3_DUTY_CYCLE => 0.500,
-         CLKOUT4_DUTY_CYCLE => 0.500,
-         CLKOUT5_DUTY_CYCLE => 0.500,
-	 SIM_DEVICE         => "SPARTAN6",
-         COMPENSATION       => "INTERNAL",
-         DIVCLK_DIVIDE      => 1,       -- C_DIVCLK_DIVIDE,
-         CLKFBOUT_MULT      => 13,      -- C_CLKFBOUT_MULT,
-</code>
-Is there a better way to fix this? Or is this the highest speed that can be used with newer MIG versions.