de     

This is an old revision of the document!


Standalone applications

In order to implement standalone applications the Firmware and the Bitstream have to be stored in non-volatile memory. At power-on the USB controller boots the Firmware from EEPROM or Flash and the Firmware configures the FPGA using a Bitstream stored in Flash.

The Default Firmwares for Series 2 FPGA Boards always support this start-up mode. This page describes how standalone functionality can be enabled in user defined Firmware.

Standalone Firmware for the EZ-USB FX2

On FX2 based FPGA Boards the standalone functionality is enabled by two macros in the Firmware source code:

ENABLE_FLASH;
ENABLE_FLASH_BITSTREAM;

The first macro enables flash support and the second one enables automatic FPGA configuration if the Firmware finds a Bitstream in Flash at start-up. These macros must appear between

#include[ztex-conf.h]

and

#include[ztex.h]

Standalone Firmware for the EZ-USB FX3

On FX3 based FPGA Boards the Flash support is always enabled. Automatic FPGA configuration is enabled by default, but can be disabled by

#define DISABLE_FLASH_CONFIG

Loading the Bitstream

There are several ways to upload the Bitstream to the Flash memory:

Hints for Vivado

With the default bitstream settings of Vivado configuration from SPI Flash may not work. The required setting can be found in the constraints file constraints/usb-fpga-2.xdc of the SDK

set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]  
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design] ;# (optional)

By default, Xilinx Series 7 FPGA's read the data at the wrong edge which means that the clock speed must be halved. For maximum configuration speed, you can enforce reading at the falling edge using the constraints

set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]  
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design] ;# (optional)
 
en/ztex_boards/ztex_fpga_boards/standalone.1648026609.txt.gz · Last modified: 2022/03/23 09:10 by stefan
 
Recent changes RSS feed Creative Commons License Powered by PHP Debian Driven by DokuWiki
[ZTEX Home] [Imprint] [Privacy policy]