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--- en:ztex_boards:ztex_fpga_boards:standalone [2022/04/01 08:46] – [Hints for Vivado] stefan
+++ en:ztex_boards:ztex_fpga_boards:standalone [2023/06/23 20:25] (current) – Updated recommended bitstream settings stefan
@@ Line 28: / Line 28: @@
   * FX2 based Series 2 FPGA Boaords: Through JTAG using [[en:ztex_boards:ztex_fpga_boards:indirect_flash_programming|indirect programming]]
 ===== Hints for Vivado =====
-With the default bitstream settings of Vivado configuration from SPI Flash may not work. The required setting can be found in the constraints file ''constraints/usb-fpga-2.xdc'' of the SDK
+FPGA configuration from SPI Flash may not work with default bitstream settings of Vivado. The recommended settings for bitstream generation are listed below and also can be found in the constraints file ''constraints/usb-fpga-2.xdc'' of the SDK:
 <code tcl>
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS true [current_design] ;# (optional)
+set_property BITSTREAM.CONFIG.CCLKPIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.INITPIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.M0PIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.M1PIN PULLDOWN [current_design]
+set_property BITSTREAM.CONFIG.M2PIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
 </code>
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