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| en:ztex_boards:ztex_fpga_boards:usb_powering [2011/12/07 22:19] – 84.181.93.233 | en:ztex_boards:ztex_fpga_boards:usb_powering [2016/09/15 08:33] – stefan |
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| ====== USB Powering ====== | ====== USB Powering ====== |
| | Most [[http://www.ztex.de/usb-fpga-2/|Sereies 2 FPGA Boards]] can be powered via USB. Whether the bus deliver sufficient current depends form the application the memory usage (RAM and controller take about 1W) and the USB specification. |
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| On Experimental Boards [[http://www.ztex.de/usb-fpga-1/exp-1.2.e.html|1.2]] and [[http://www.ztex.de/usb-fpga-1/exp-1.3.e.html|1.3]] and [[http://www.ztex.de/usb-fpga-1/pwr-1.1.e.html|Power Supply Modules 1.1]] FPGA Boards can be easily supplied by USB by connecting pins B2 and and A1 on the Experimental Board I/O connector or by connecting pins A1, B2, C1, D1 on the FPGA Board I/O connector. | Whether / how USB powering is supported is listed in the following table |
| | ^ FPGA Board ^ Power source selection ^ comments ^ |
| | | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Module 2.16]] | no | USB powering not supported | |
| | | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.14.e.html|USB-FPGA Module 2.14]] | automatically | USB 3.0 delivers sufficient power for small applications including RAM | |
| | | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html|USB-FPGA Module 2.13]] | by soldering a 0Ω | not recommended because USB 2.0 usually deliver insufficient power | |
| | | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.04.e.html|USB-FPGA Module 2.04]] | by soldering a 0Ω | USB 2.0 usually deliver insufficient power if RAM is used | |
| | | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.01.e.html|USB-FPGA Module 2.01]] | by jumper | USB 2.0 usually deliver sufficient power | |
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| If devices are powered by USB is must be ensured that the power requirement is within the USB specifications. USB standard guarntees 0.5W and allows up to 2.5W. | |
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| DDR SDRAM on [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|USB-FPGA Modules 1.11]] requires about 1.8W and DDR2 SDRAM on [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|USB-FPGA Modules 1.15]] about 1.4W at maximum frequency. A lot of power can be saved by reducing memory clock frequency and by turning off the parallel termination. E.g. at a memory frequency of 133 MHz the bandwidth is still 532 MByte/s which is sufficient for the most applications. | |
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